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| author | Clifford Wolf <clifford@clifford.at> | 2019-10-22 17:36:54 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-10-22 17:36:54 +0200 |
| commit | a3a7bb9bf7160d434db7a4737e68f6b015b221ef (patch) | |
| tree | 752e1d94d353e6969cd0c7f324ee3e819e435e2d | |
| parent | 5025aab8c9b47e2a201f7ffd494475882db92398 (diff) | |
| parent | 3b405d985e789ecf0082f724d2d62d3752e4b60c (diff) | |
| download | yosys-a3a7bb9bf7160d434db7a4737e68f6b015b221ef.tar.gz yosys-a3a7bb9bf7160d434db7a4737e68f6b015b221ef.tar.bz2 yosys-a3a7bb9bf7160d434db7a4737e68f6b015b221ef.zip | |
Merge pull request #1452 from nakengelhardt/fix_dsp_mem_reg
Call memory_dff before DSP mapping to reserve registers (fixes #1447)
| -rw-r--r-- | techlibs/ice40/synth_ice40.cc | 1 | ||||
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index b66c6bf57..c942126e1 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -273,6 +273,7 @@ struct SynthIce40Pass : public ScriptPass run("opt_expr"); run("opt_clean"); if (help_mode || dsp) { + run("memory_dff"); run("techmap -map +/mul2dsp.v -map +/ice40/dsp_map.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 " "-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 " "-D DSP_NAME=$__MUL16X16", "(if -dsp)"); diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index f13740865..6f8254b59 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -341,6 +341,7 @@ struct SynthXilinxPass : public ScriptPass if (check_label("map_dsp", "(skip if '-nodsp')")) { if (!nodsp || help_mode) { + run("memory_dff"); // xilinx_dsp will merge registers, reserve memory port registers first // NB: Xilinx multipliers are signed only run("techmap -map +/mul2dsp.v -map +/xilinx/dsp_map.v -D DSP_A_MAXWIDTH=25 " "-D DSP_A_MAXWIDTH_PARTIAL=18 -D DSP_B_MAXWIDTH=18 " // Partial multipliers are intentionally |