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| author | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-04 08:27:49 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-17 17:10:42 +0200 |
| commit | 53bc499a907cc3bfbeb91866d8839286ae0dfdf1 (patch) | |
| tree | eb96e0db172be4b5af1511d853e02e400141a7aa | |
| parent | d37cd267a56295737e95f5bc5e6f446c27605639 (diff) | |
| download | yosys-53bc499a907cc3bfbeb91866d8839286ae0dfdf1.tar.gz yosys-53bc499a907cc3bfbeb91866d8839286ae0dfdf1.tar.bz2 yosys-53bc499a907cc3bfbeb91866d8839286ae0dfdf1.zip | |
Clean verilog code from not used define block
| -rw-r--r-- | tests/xilinx/shifter.v | 6 | ||||
| -rw-r--r-- | tests/xilinx/tribuf.v | 6 |
2 files changed, 0 insertions, 12 deletions
diff --git a/tests/xilinx/shifter.v b/tests/xilinx/shifter.v index c55632552..04ae49d83 100644 --- a/tests/xilinx/shifter.v +++ b/tests/xilinx/shifter.v @@ -9,14 +9,8 @@ in always @(posedge clk)
begin
-`ifndef BUG
out <= out >> 1;
out[7] <= in;
-`else
-
- out <= out << 1;
- out[7] <= in;
-`endif
end
endmodule
diff --git a/tests/xilinx/tribuf.v b/tests/xilinx/tribuf.v index 3fa6eb6c6..75149d8ba 100644 --- a/tests/xilinx/tribuf.v +++ b/tests/xilinx/tribuf.v @@ -2,15 +2,9 @@ module tristate (en, i, o); input en; input i; output reg o; -`ifndef BUG always @(en or i) o <= (en)? i : 1'bZ; -`else - - always @(en or i) - o <= (en)? ~i : 1'bZ; -`endif endmodule |