remove not needed top module

2 files changed, 2 insertions, 20 deletions

diff --git a/tests/xilinx/fsm.v b/tests/xilinx/fsm.v
index 0605bd102..368fbaace 100644
--- a/tests/xilinx/fsm.v
+++ b/tests/xilinx/fsm.v
@@ -52,22 +52,4 @@
  endcase

  end

 

- endmodule

-

- module top (

-input clk,

-input rst,

-input a,

-input b,

-output g0,

-output g1

-);

-

-fsm u_fsm ( .clock(clk),

-            .reset(rst),

-            .req_0(a),

-            .req_1(b),

-            .gnt_0(g0),

-            .gnt_1(g1));

-

 endmodule

diff --git a/tests/xilinx/fsm.ys b/tests/xilinx/fsm.ys
index 3b73891c2..a9e94c2c0 100644
--- a/tests/xilinx/fsm.ys
+++ b/tests/xilinx/fsm.ys
@@ -1,10 +1,10 @@
 read_verilog fsm.v
-hierarchy -top top
+hierarchy -top fsm
 proc
 flatten
 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
+cd fsm # Constrain all select calls below inside the top module
 
 select -assert-count 1 t:BUFG
 select -assert-count 5 t:FDRE