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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-30 19:57:26 -0700 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-17 17:10:42 +0200 |
| commit | 3b4408432073ec4d9a2b8995b8e08a5bf6175f39 (patch) | |
| tree | 3c33accdb29d12c8cd31855fd3e61da41fe79625 | |
| parent | 8422ad3e3a5db583f59906f8a5d81587dd777f6d (diff) | |
| download | yosys-3b4408432073ec4d9a2b8995b8e08a5bf6175f39.tar.gz yosys-3b4408432073ec4d9a2b8995b8e08a5bf6175f39.tar.bz2 yosys-3b4408432073ec4d9a2b8995b8e08a5bf6175f39.zip | |
Add -assert
| -rw-r--r-- | tests/xilinx/counter.ys | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/xilinx/counter.ys b/tests/xilinx/counter.ys index b602b74d7..3bb3a8eb0 100644 --- a/tests/xilinx/counter.ys +++ b/tests/xilinx/counter.ys @@ -2,7 +2,7 @@ read_verilog counter.v hierarchy -top top proc flatten -equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module |