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| author | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-18 11:18:53 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-18 11:18:53 +0200 |
| commit | ab98f2dccf52a1bba396fe313ea0670603dc45ca (patch) | |
| tree | 789e5258c76a6331efb2eee8bd4fa74b7b980e4d | |
| parent | 56f94826753c1f26c9026493a40ecef14806d779 (diff) | |
| download | yosys-ab98f2dccf52a1bba396fe313ea0670603dc45ca.tar.gz yosys-ab98f2dccf52a1bba396fe313ea0670603dc45ca.tar.bz2 yosys-ab98f2dccf52a1bba396fe313ea0670603dc45ca.zip | |
fix yosys path
| -rw-r--r-- | tests/arch/xilinx/macc.sh | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/tests/arch/xilinx/macc.sh b/tests/arch/xilinx/macc.sh index 86e4c2bb6..2272679ee 100644 --- a/tests/arch/xilinx/macc.sh +++ b/tests/arch/xilinx/macc.sh @@ -1,3 +1,3 @@ -../../yosys -qp "synth_xilinx -top macc2; rename -top macc2_uut" macc.v -o macc_uut.v -iverilog -o test_macc macc_tb.v macc_uut.v macc.v ../../techlibs/xilinx/cells_sim.v +../../../yosys -qp "synth_xilinx -top macc2; rename -top macc2_uut" macc.v -o macc_uut.v +iverilog -o test_macc macc_tb.v macc_uut.v macc.v ../../../techlibs/xilinx/cells_sim.v vvp -N ./test_macc |