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| author | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-18 12:20:35 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-18 12:20:35 +0200 |
| commit | 477702b8c91bb7780ac80b25c8ad659cd40b445d (patch) | |
| tree | 8d11b79822187dbac8b03c7314eb6b4d8959a7f1 | |
| parent | 5603595e5c0efd2afc9ba810e6e5992e5d81d44c (diff) | |
| download | yosys-477702b8c91bb7780ac80b25c8ad659cd40b445d.tar.gz yosys-477702b8c91bb7780ac80b25c8ad659cd40b445d.tar.bz2 yosys-477702b8c91bb7780ac80b25c8ad659cd40b445d.zip | |
Remove not needed tests
| -rw-r--r-- | tests/arch/ice40/alu.v | 19 | ||||
| -rw-r--r-- | tests/arch/ice40/alu.ys | 11 | ||||
| -rw-r--r-- | tests/arch/ice40/div_mod.v | 13 | ||||
| -rw-r--r-- | tests/arch/ice40/div_mod.ys | 9 |
4 files changed, 0 insertions, 52 deletions
diff --git a/tests/arch/ice40/alu.v b/tests/arch/ice40/alu.v deleted file mode 100644 index f82cc2e21..000000000 --- a/tests/arch/ice40/alu.v +++ /dev/null @@ -1,19 +0,0 @@ -module top ( - input clock, - input [31:0] dinA, dinB, - input [2:0] opcode, - output reg [31:0] dout -); - always @(posedge clock) begin - case (opcode) - 0: dout <= dinA + dinB; - 1: dout <= dinA - dinB; - 2: dout <= dinA >> dinB; - 3: dout <= $signed(dinA) >>> dinB; - 4: dout <= dinA << dinB; - 5: dout <= dinA & dinB; - 6: dout <= dinA | dinB; - 7: dout <= dinA ^ dinB; - endcase - end -endmodule diff --git a/tests/arch/ice40/alu.ys b/tests/arch/ice40/alu.ys deleted file mode 100644 index bd859efc4..000000000 --- a/tests/arch/ice40/alu.ys +++ /dev/null @@ -1,11 +0,0 @@ -read_verilog alu.v -hierarchy -top top -proc -flatten -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 62 t:SB_CARRY -select -assert-count 32 t:SB_DFF -select -assert-count 655 t:SB_LUT4 -select -assert-none t:SB_CARRY t:SB_DFF t:SB_LUT4 %% t:* %D diff --git a/tests/arch/ice40/div_mod.v b/tests/arch/ice40/div_mod.v deleted file mode 100644 index 64a36707d..000000000 --- a/tests/arch/ice40/div_mod.v +++ /dev/null @@ -1,13 +0,0 @@ -module top -( - input [3:0] x, - input [3:0] y, - - output [3:0] A, - output [3:0] B - ); - -assign A = x % y; -assign B = x / y; - -endmodule diff --git a/tests/arch/ice40/div_mod.ys b/tests/arch/ice40/div_mod.ys deleted file mode 100644 index 821d6c301..000000000 --- a/tests/arch/ice40/div_mod.ys +++ /dev/null @@ -1,9 +0,0 @@ -read_verilog div_mod.v -hierarchy -top top -flatten -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 59 t:SB_LUT4 -select -assert-count 41 t:SB_CARRY -select -assert-none t:SB_LUT4 t:SB_CARRY %% t:* %D |