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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-30 14:17:59 -0700 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-17 17:10:02 +0200 |
| commit | a12801843bb400bba8f2f8ce99a3f524ac05b7e8 (patch) | |
| tree | 87290adc027de9a64e47ed2d710bb7b91e75db93 | |
| parent | eded90b6b42117ba427469a6100c74e708c4f142 (diff) | |
| download | yosys-a12801843bb400bba8f2f8ce99a3f524ac05b7e8.tar.gz yosys-a12801843bb400bba8f2f8ce99a3f524ac05b7e8.tar.bz2 yosys-a12801843bb400bba8f2f8ce99a3f524ac05b7e8.zip | |
Add comment for lack of tristate logic pointing to #1225
| -rw-r--r-- | tests/xilinx/tribuf.ys | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/xilinx/tribuf.ys b/tests/xilinx/tribuf.ys index 76b00647d..696be2620 100644 --- a/tests/xilinx/tribuf.ys +++ b/tests/xilinx/tribuf.ys @@ -7,6 +7,6 @@ synth equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -#Xilinx Vivado synthesizes OBUFT cell for this case. Need support it. +# TODO :: Tristate logic not yet supported; see https://github.com/YosysHQ/yosys/issues/1225 select -assert-count 1 t:$_TBUF_ select -assert-none t:$_TBUF_ %% t:* %D |