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| author | SergeyDegtyar <sndegtyar@gmail.com> | 2019-09-17 11:53:49 +0300 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-17 17:10:02 +0200 |
| commit | 305672170bcd6346bebbb01c843225fe0392a37d (patch) | |
| tree | 069825d0093117bf650ae2401377f378452e8f21 | |
| parent | bb70eb977dc29dbfe8cfb9af847046f387bd54b2 (diff) | |
| download | yosys-305672170bcd6346bebbb01c843225fe0392a37d.tar.gz yosys-305672170bcd6346bebbb01c843225fe0392a37d.tar.bz2 yosys-305672170bcd6346bebbb01c843225fe0392a37d.zip | |
adffs test update (equiv_opt -multiclock)
| -rw-r--r-- | tests/xilinx/adffs.ys | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/tests/xilinx/adffs.ys b/tests/xilinx/adffs.ys index 38c82a36f..961e08ae9 100644 --- a/tests/xilinx/adffs.ys +++ b/tests/xilinx/adffs.ys @@ -1,13 +1,14 @@ read_verilog adffs.v proc -async2sync # converts async flops to a 'sync' variant clocked by a 'super'-clock flatten -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -multiclock -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG -select -assert-count 3 t:FDRE +select -assert-count 2 t:FDCE +select -assert-count 1 t:FDRE select -assert-count 1 t:FDRE_1 -select -assert-count 5 t:LUT2 -select -assert-none t:BUFG t:FDRE t:FDRE_1 t:LUT2 %% t:* %D +select -assert-count 1 t:LUT1 +select -assert-count 2 t:LUT2 +select -assert-none t:BUFG t:FDCE t:FDRE t:FDRE_1 t:LUT1 t:LUT2 %% t:* %D |