| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Added extractinv pass | Marcin Kościelnicki | 2019-09-19 | 1 | -0/+6 |
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| * | Merge pull request #1312 from YosysHQ/xaig_arrival | Eddie Hung | 2019-09-05 | 1 | -8/+5 |
| |\ | | | | | Allow arrival times of sequential outputs to be specified to abc9 | ||||
| | * | Merge remote-tracking branch 'origin/master' into xaig_arrival | Eddie Hung | 2019-08-30 | 1 | -14/+14 |
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| | * \ | Merge remote-tracking branch 'origin/master' into xaig_arrival | Eddie Hung | 2019-08-30 | 1 | -1/+1 |
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| | * \ \ | Merge remote-tracking branch 'origin/master' into xaig_arrival | Eddie Hung | 2019-08-28 | 1 | -0/+15 |
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| | * \ \ \ | Merge remote-tracking branch 'origin/master' into xaig_arrival | Eddie Hung | 2019-08-23 | 1 | -3/+6 |
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| | * | | | | | Add (* abc_arrival=<int> *) doc | Eddie Hung | 2019-08-20 | 1 | -0/+5 |
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| | * | | | | | Deprecate `abc_scc_break` attribute | Eddie Hung | 2019-08-20 | 1 | -8/+0 |
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| * | | | | | | Update README.md | Clifford Wolf | 2019-09-05 | 1 | -1/+2 |
| | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | | | | | Rename conflicting wires on flatten/techmap, add "hierconn" attribute, fixes ↵ | Clifford Wolf | 2019-09-05 | 1 | -0/+3 |
| | |_|_|_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | #1220 Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | | | | Merge pull request #1340 from YosysHQ/eddie/abc_no_clean | Eddie Hung | 2019-08-30 | 1 | -17/+17 |
| |\ \ \ \ \ | |_|_|_|/ |/| | | | | abc9 to not call "clean" at end of run (often called outside) | ||||
| | * | | | | Group abc_* attribute doc with other attributes | Eddie Hung | 2019-08-29 | 1 | -17/+17 |
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| * / | | | Format `-pwires` | Eddie Hung | 2019-08-30 | 1 | -1/+1 |
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| * | | | Mention clkbuf_inhibit can be overridden | Eddie Hung | 2019-08-23 | 1 | -7/+8 |
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| * | | | Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-23 | 1 | -3/+23 |
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| | * | | Make macOS depenency clear | Miodrag Milanovic | 2019-08-23 | 1 | -2/+5 |
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| | * | | Bump year in copyright notice | Clifford Wolf | 2019-08-22 | 1 | -1/+1 |
| | |/ | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | Clarify with 'only' | Eddie Hung | 2019-08-19 | 1 | -1/+1 |
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| | * | Update doc | Eddie Hung | 2019-08-19 | 1 | -3/+4 |
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| | * | Add doc for abc_* attributes | Eddie Hung | 2019-08-16 | 1 | -0/+16 |
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| * | | README updates | Marcin Kościelnicki | 2019-08-13 | 1 | -0/+14 |
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| * | Update README to use "read" instead of "read_verilog" | Clifford Wolf | 2019-07-29 | 1 | -48/+19 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Add support for reading gzip'd input files | David Shah | 2019-07-26 | 1 | -3/+3 |
| | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | Updated FreeBSD dependencies in README.md | Roman-Parise | 2019-07-14 | 1 | -1/+1 |
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| * | Add "read_verilog -pwires" feature, closes #1106 | Clifford Wolf | 2019-06-19 | 1 | -0/+4 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Add defaultvalue attribute | Clifford Wolf | 2019-06-19 | 1 | -0/+4 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | README.md: Missing formatting for <tag> | Tux3 | 2019-06-04 | 1 | -1/+1 |
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| * | Refactor hierarchy wand/wor handling | Clifford Wolf | 2019-05-28 | 1 | -1/+1 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | update README.md with wand/wor information | Stefan Biereigel | 2019-05-27 | 1 | -2/+2 |
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| * | Add $stop to documentation | Clifford Wolf | 2019-05-09 | 1 | -3/+4 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Update README | Clifford Wolf | 2019-05-04 | 1 | -5/+1 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Add specify support to README | Clifford Wolf | 2019-04-23 | 1 | -0/+5 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Format some names using inline code | Eddie Hung | 2019-04-23 | 1 | -2/+2 |
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| * | Fix spelling | Eddie Hung | 2019-04-23 | 1 | -1/+1 |
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| * | Merge pull request #905 from christian-krieg/feature/python_bindings | Clifford Wolf | 2019-04-22 | 1 | -4/+5 |
| |\ | | | | | Feature/python bindings | ||||
| | * | Changed filesystem dependency to boost instead of experimental std library | Benedikt Tutzer | 2019-04-04 | 1 | -1/+1 |
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| | * | Added dependencies to README and travis configuration | Benedikt Tutzer | 2019-04-03 | 1 | -4/+5 |
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| * | | Add "noblackbox" attribute | Clifford Wolf | 2019-04-21 | 1 | -1/+6 |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | New behavior for front-end handling of whiteboxes | Clifford Wolf | 2019-04-20 | 1 | -0/+3 |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | Add "whitebox" attribute, add "read_verilog -wb" | Clifford Wolf | 2019-04-18 | 1 | -0/+4 |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | README: fix some incorrect quoting. | whitequark | 2019-04-15 | 1 | -2/+2 |
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| * | Add "hdlname" attribute | Clifford Wolf | 2019-03-26 | 1 | -0/+3 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Add note about test requirements in README | Felix Vietmeyer | 2019-03-16 | 1 | -1/+4 |
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| * | Only run derive on blackbox modules when ports have dynamic size | Clifford Wolf | 2019-03-02 | 1 | -0/+3 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Minor improvements in README | Clifford Wolf | 2019-03-01 | 1 | -3/+16 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Fix typographical and grammatical errors and inconsistencies. | whitequark | 2019-01-02 | 1 | -9/+9 |
| | | | | | | | | | | | | | The initial list of hits was generated with the codespell command below, and each hit was evaluated and fixed manually while taking context into consideration. DIRS="kernel/ frontends/ backends/ passes/ techlibs/" DIRS="${DIRS} libs/ezsat/ libs/subcircuit" codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint More hits were found by looking through comments and strings manually. | ||||
| * | Merge pull request #659 from rubund/sv_interfaces | Clifford Wolf | 2018-10-18 | 1 | -0/+3 |
| |\ | | | | | Support for SystemVerilog interfaces and modports | ||||
| | * | Documentation improvements etc. | Ruben Undheim | 2018-10-13 | 1 | -0/+3 |
| | | | | | | | | | | | | | | | | | | | - Mention new feature in the SystemVerilog section in the README file - Commented changes much better - Rename a few signals to make it clearer - Prevent warning for unused signals in an easier way - Add myself as copyright holder to 2 files - Fix one potential memory leak (delete 'wire' if not in modport) | ||||
| * | | We have 2018 now | Clifford Wolf | 2018-10-16 | 1 | -1/+1 |
| |/ | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Fix Cygwin build and document needed packages | Miodrag Milanovic | 2018-09-19 | 1 | -0/+4 |
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index : iCE40/yosys | |
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