diff options
Diffstat (limited to 'testsuite')
257 files changed, 6343 insertions, 16 deletions
diff --git a/testsuite/gna/bug0100/emptyrec.vhdl b/testsuite/gna/bug0100/emptyrec.vhdl new file mode 100644 index 000000000..7c771fb28 --- /dev/null +++ b/testsuite/gna/bug0100/emptyrec.vhdl @@ -0,0 +1,11 @@ +entity emptyrec is + port ( + clk_i : in bit + ); +end emptyrec; + +architecture arch of emptyrec is + type t_counter_config is record + end record; +begin +end arch; diff --git a/testsuite/gna/bug0100/testsuite.sh b/testsuite/gna/bug0100/testsuite.sh index d9e2210c4..cd3799b61 100755 --- a/testsuite/gna/bug0100/testsuite.sh +++ b/testsuite/gna/bug0100/testsuite.sh @@ -33,6 +33,7 @@ analyze_failure --force-analysis name4.vhdl analyze_failure --force-analysis inst2.vhdl analyze_failure arr_err1.vhdl analyze_failure --force-analysis oper1.vhdl +analyze_failure --force-analysis emptyrec.vhdl if analyze_failure --force-analysis notype1.vhdl 2>&1 | grep -q "indexed name"; then : diff --git a/testsuite/gna/issue2065/dual_port_ram.vhdl b/testsuite/gna/issue2065/dual_port_ram.vhdl new file mode 100644 index 000000000..7039d5c8f --- /dev/null +++ b/testsuite/gna/issue2065/dual_port_ram.vhdl @@ -0,0 +1,107 @@ +-- dual_port_ram.vhd +-- This file is part of bladeRF-wiphy. +-- +-- Copyright (C) 2021 Nuand, LLC. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License along +-- with this program; if not, write to the Free Software Foundation, Inc., +-- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity dual_port_ram is + generic( + ADDR_BITS : in natural := 6; + DATA_BITS : in natural := 32 + ); + port( + clock : in std_logic; + reset : in std_logic; + + acc : in std_logic; + solo : in std_logic; + write : in std_logic; + + addr_a : in std_logic_vector(ADDR_BITS-1 downto 0); + in_a : in std_logic_vector(DATA_BITS-1 downto 0); + data_a : out std_logic_vector(DATA_BITS-1 downto 0); + + addr_b : in std_logic_vector(ADDR_BITS-1 downto 0); + in_b : in std_logic_vector(DATA_BITS-1 downto 0); + data_b : out std_logic_vector(DATA_BITS-1 downto 0) + ); +end entity; + +architecture arch of dual_port_ram is + type ram_t is array(natural range <>) of std_logic_vector(DATA_BITS-1 downto 0); + + signal ram : ram_t((2**ADDR_BITS-1) downto 0); +begin + sync : process(clock, reset) + variable add_a, add_b : integer; + begin + if (reset = '1') then + for i in ram'range loop + ram(i) <= ( others => '0' ); + end loop; + elsif (rising_edge(clock)) then + if (acc = '1') then + add_a := to_integer(unsigned(addr_a)); + add_b := to_integer(unsigned(addr_b)); + + if (write = '1') then + ram(add_a) <= in_a; + data_a <= in_a; + if (solo = '0') then + ram(add_b) <= in_b; + data_b <= in_b; + else + data_b <= ( others => '0' ); + end if; + else + data_a <= ram(add_a); + if (solo = '0') then + data_b <= ram(add_b); + else + data_b <= ( others => '0' ); + end if; + end if; + end if; + + end if; + end process; +end architecture; + +architecture synth of dual_port_ram is + type ram_t is array(natural range <>) of std_logic_vector(DATA_BITS-1 downto 0); + signal ram : ram_t((2**ADDR_BITS-1) downto 0); +begin + sync : process(clock, reset) + variable addra : integer; + variable addrb : integer; + begin + if (rising_edge(clock)) then + addra := to_integer(unsigned(addr_a)); + addrb := to_integer(unsigned(addr_b)); + if (write = '1') then + ram(addra) <= in_a; + ram(addrb) <= in_a; + end if; + data_a <= ram(addra); + data_b <= ram(addrb); + end if; + end process; + +end architecture synth; diff --git a/testsuite/gna/issue2065/fft.vhdl b/testsuite/gna/issue2065/fft.vhdl new file mode 100644 index 000000000..857e42203 --- /dev/null +++ b/testsuite/gna/issue2065/fft.vhdl @@ -0,0 +1,606 @@ +-- fft.vhd +-- This file is part of bladeRF-wiphy. +-- +-- Copyright (C) 2021 Nuand, LLC. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License along +-- with this program; if not, write to the Free Software Foundation, Inc., +-- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + use ieee.math_real.all; + +entity fft is + generic( + PARALLEL : in natural := 4; + N : in natural := 8; + BITS : in natural := 16 + ); + port( + clock : in std_logic; + reset : in std_logic; + + inverse : in std_logic; + in_real : in std_logic_vector(BITS-1 downto 0); + in_imag : in std_logic_vector(BITS-1 downto 0); + in_valid : in std_logic; + in_sop : in std_logic; + in_eop : in std_logic; + + out_real : out std_logic_vector(BITS-1 downto 0); + out_imag : out std_logic_vector(BITS-1 downto 0); + out_error : out std_logic; + out_valid : out std_logic; + out_sop : out std_logic; + out_eop : out std_logic + ); +end entity; + +architecture mult of fft is + type fft_out_t is record + out_real : std_logic_vector(BITS-1 downto 0); + out_imag : std_logic_vector(BITS-1 downto 0); + out_error : std_logic; + out_valid : std_logic; + out_sop : std_logic; + out_eop : std_logic; + end record; + type fft_out_arr_t is array(natural range <>) of fft_out_t; + + signal fft_out : fft_out_arr_t(0 to PARALLEL-1); + + signal in_idx : natural range 0 to PARALLEL; + signal out_idx : natural range 0 to PARALLEL; + signal in_mask : std_logic_vector(PARALLEL-1 downto 0); + +begin + + sync : process(clock, reset) + variable tmp_idx : natural range 0 to PARALLEL; + begin + if (reset = '1') then + in_idx <= 0; + out_idx <= 0; + in_mask <= std_logic_vector(to_unsigned(1, PARALLEL)); + elsif (rising_edge(clock)) then + if (in_eop = '1') then + if (in_idx = PARALLEL-1) then + tmp_idx := 0; + else + tmp_idx := tmp_idx + 1; + end if; + in_mask <= std_logic_vector(shift_left(to_unsigned(1, PARALLEL), tmp_idx)); + in_idx <= tmp_idx; + end if; + if (out_eop = '1') then + if (out_idx = PARALLEL-1) then + out_idx <= 0; + else + out_idx <= out_idx + 1; + end if; + end if; + end if; + end process; + + U_fft_gen: for i in 0 to PARALLEL-1 generate + U_fft_inst : entity work.fft(arch) + generic map( + N => N, + BITS => BITS + ) port map( + clock => clock, + reset => reset, + inverse => inverse, + in_real => in_real, + in_imag => in_imag, + in_valid => in_mask(i) and in_valid, + in_sop => in_mask(i) and in_sop, + in_eop => in_mask(i) and in_eop, + out_real => fft_out(i).out_real, + out_imag => fft_out(i).out_imag, + out_error => fft_out(i).out_error, + out_valid => fft_out(i).out_valid, + out_sop => fft_out(i).out_sop, + out_eop => fft_out(i).out_eop + ); + end generate; + + process(fft_out, out_idx) + begin + out_real <= fft_out(out_idx).out_real; + out_imag <= fft_out(out_idx).out_imag; + out_error <= fft_out(out_idx).out_error; + out_valid <= fft_out(out_idx).out_valid; + out_sop <= fft_out(out_idx).out_sop; + out_eop <= fft_out(out_idx).out_eop; + end process; + +end architecture mult; + +architecture arch of fft is + constant ADDR_BITS : integer := integer(ceil(log2(real(N)))); + constant NUM_STAGES : integer := integer(ceil(log2(real(N)))); + constant POSTBITS : integer := 0; + function PIPELINE_BITS return integer is + begin + return BITS + NUM_STAGES; + end function; + + constant DATA_BITS : integer := PIPELINE_BITS*2; + + type complex_sample_t is record + i : signed(PIPELINE_BITS-1 downto 0); + q : signed(PIPELINE_BITS-1 downto 0); + end record; + + type complex_sample_arr_t is array(natural range <>) of complex_sample_t; + function NULL_COMPLEX_SAMPLE return complex_sample_t is + variable ret : complex_sample_t; + begin + ret.i := ( others => '0' ); + ret.q := ( others => '0' ); + return(ret); + end function; + + type mem_bank_ctrl_t is record + acc : std_logic; + write : std_logic; + solo : std_logic; + + addr_a : std_logic_vector(ADDR_BITS-1 downto 0); + in_a : std_logic_vector(DATA_BITS-1 downto 0); + data_a : std_logic_vector(DATA_BITS-1 downto 0); + addr_b : std_logic_vector(ADDR_BITS-1 downto 0); + in_b : std_logic_vector(DATA_BITS-1 downto 0); + data_b : std_logic_vector(DATA_BITS-1 downto 0); + end record; + + function slv_to_cst(x : std_logic_vector) return complex_sample_t is + variable ret : complex_sample_t; + begin + ret.i := resize(signed(x(x'high-1 downto PIPELINE_BITS)), PIPELINE_BITS); + ret.q := resize(signed(x(PIPELINE_BITS-1 downto 0)), PIPELINE_BITS); + return(ret); + end function; + + function reverse_bit_order(x : unsigned) return std_logic_vector is + variable ret : std_logic_vector(x'range); + begin + for i in x'range loop + ret(i) := x(x'high - i); + end loop; + return(ret); + end function; + + function NULL_MEM_BANK_CTRL return mem_bank_ctrl_t is + variable ret : mem_bank_ctrl_t; + begin + ret.acc := '0'; + ret.solo := '0'; + ret.write := '0'; + ret.addr_a := ( others => '0' ); + ret.in_a := ( others => '0' ); + ret.data_a := ( others => '0' ); + ret.addr_b := ( others => '0' ); + ret.in_b := ( others => '0' ); + ret.data_b := ( others => '0' ); + return(ret); + end function; + + type fsm_t is (IDLE, LOAD, FIRST_STAGE, RUN_STAGE, WAIT_STAGE, READ_OUT, STOP, RESET_STAGE); + type r_fsm_t is (IDLE, PASSTHROUGH, MEM_READ); + + type mem_bank_ctrl_arr_t is array(natural range <>) of mem_bank_ctrl_t; + type state_t is record + fsm : fsm_t; + rfsm : r_fsm_t; + count : integer range 0 to N+1; + bf_ready : std_logic; + iter : integer range 0 to N+2; + + mbc : mem_bank_ctrl_arr_t(1 downto 0); + buffer_idx : std_logic; + write_idx : unsigned(ADDR_BITS-1 downto 0); + + stage : integer range 0 to N; + twiddle_idx : unsigned(ADDR_BITS-2 downto 0); + tw : complex_sample_t; + + sop : std_logic; + eop : std_logic; + N2_sample : complex_sample_t; + N2_sample_r : complex_sample_t; + out_sample : complex_sample_t; + valid : std_logic; + end record; + + type butter_fly_t is record + A, B, TW : complex_sample_t; + addr_a : std_logic_vector(ADDR_BITS-1 downto 0); + addr_b : std_logic_vector(ADDR_BITS-1 downto 0); + valid : std_logic; + end record; + + type butter_fly_arr_t is array(natural range <>) of butter_fly_t; + signal bf_pl : butter_fly_arr_t(0 to 3); + + function NULL_BF_T return butter_fly_t is + variable ret : butter_fly_t; + begin + ret.A := NULL_COMPLEX_SAMPLE; + ret.B := NULL_COMPLEX_SAMPLE; + ret.TW := NULL_COMPLEX_SAMPLE; + ret.addr_a := ( others => '0' ); + ret.addr_b := ( others => '0' ); + ret.valid := '0'; + return(ret); + end function; + + function shift_sample(x : complex_sample_t ; enable : std_logic) return complex_sample_t is + variable ret : complex_sample_t; + begin + if (enable = '0') then + ret.i := shift_right(x.i, POSTBITS*NUM_STAGES); + ret.q := shift_right(x.q, POSTBITS*NUM_STAGES); + else + ret.i := shift_right(x.i, NUM_STAGES+POSTBITS*NUM_STAGES); + ret.q := shift_right(x.q, NUM_STAGES+POSTBITS*NUM_STAGES); + end if; + return(ret); + end function; + + function NULL_STATE_T return state_t is + variable ret : state_t; + begin + ret.fsm := IDLE; + ret.rfsm := IDLE; + for i in ret.mbc'range loop + ret.mbc(i) := NULL_MEM_BANK_CTRL; + end loop; + + ret.count := 0; + + ret.iter := 0; + ret.bf_ready := '0'; + + ret.buffer_idx := '0'; + ret.write_idx := ( others => '0' ); + + ret.stage := 0; + + ret.twiddle_idx := ( others => '0' ); + + ret.tw.i := ( others => '0' ); + ret.tw.q := ( others => '0' ); + + ret.sop := '0'; + ret.eop := '0'; + ret.valid := '0'; + ret.N2_sample := NULL_COMPLEX_SAMPLE; + ret.N2_sample_r := NULL_COMPLEX_SAMPLE; + ret.out_sample := NULL_COMPLEX_SAMPLE; + return(ret); + end function; + + function rc_func(x : real) return real is + begin + if (x < 0.0) then + return(ceil(x)); + else + return(floor(x)); + end if; + end function; + + function gen_roots_of_unity return complex_sample_arr_t is + variable t_s, t_c : real := 0.0; + variable ret : complex_sample_arr_t(((N/2)-1) downto 0); + begin + for i in 0 to (N/2)-1 loop + t_c := rc_func(cos(real(MATH_2_PI * real(i) / real(N))) * real(2**(BITS-1) - 1)); + t_s := rc_func(sin(real(MATH_2_PI * real(i) / real(N))) * real(2**(BITS-1) - 1)); + ret(i).i := to_signed(integer(t_c), PIPELINE_BITS); + ret(i).q := to_signed(integer(t_s), PIPELINE_BITS); + --report integer'image(i) & " = " & integer'image(integer(t_c)) & + -- " , " & integer'image(integer(t_s)) ; + end loop; + + return(ret); + end function; + + constant TLUT : complex_sample_arr_t(((N/2)-1) downto 0) := gen_roots_of_unity; + + signal current, future : state_t := NULL_STATE_T; + + signal muxed_mbc : mem_bank_ctrl_arr_t(1 downto 0); + + signal data_mbc : mem_bank_ctrl_arr_t(1 downto 0); + signal curr_data : mem_bank_ctrl_t; + + signal mix : complex_sample_t; + signal T_A, T_B : complex_sample_t; + + signal comp_mbc : mem_bank_ctrl_t; +begin + U_mem_banks: for i in 0 to 1 generate + U_mem_bank: entity work.dual_port_ram(synth) + generic map( + ADDR_BITS => ADDR_BITS, + DATA_BITS => DATA_BITS + ) + port map( + clock => clock, + reset => reset, + + acc => muxed_mbc(i).acc, + solo => muxed_mbc(i).solo, + write => muxed_mbc(i).write, + + addr_a => muxed_mbc(i).addr_a, + in_a => muxed_mbc(i).in_a, + data_a => data_mbc(i).data_a, + + addr_b => muxed_mbc(i).addr_b, + in_b => muxed_mbc(i).in_b, + data_b => data_mbc(i).data_b + ); + end generate; + + comp_mbc.addr_a <= bf_pl(3).addr_a; + comp_mbc.in_a <= std_logic_vector(T_A.i) & std_logic_vector(T_A.q); + comp_mbc.addr_b <= bf_pl(3).addr_b; + comp_mbc.in_b <= std_logic_vector(T_B.i) & std_logic_vector(T_B.q); + comp_mbc.acc <= bf_pl(3).valid; + comp_mbc.write <= bf_pl(3).valid; + comp_mbc.solo <= '0'; + + sync : process(clock, reset) + begin + if (reset = '1') then + current <= NULL_STATE_T; + bf_pl(1).addr_a <= ( others => '0' ); + bf_pl(1).addr_b <= ( others => '0' ); + bf_pl(2) <= NULL_BF_T; + bf_pl(3) <= NULL_BF_T; + elsif (rising_edge(clock)) then + current <= future; + + bf_pl(1).valid <= current.bf_ready; + bf_pl(1).addr_a <= current.mbc(0).addr_a; + bf_pl(1).addr_b <= current.mbc(0).addr_b; + bf_pl(2) <= bf_pl(1); + bf_pl(3) <= bf_pl(2); + end if; + end process; + + butterfly : process(clock, reset) + begin + if (rising_edge(clock)) then + mix.i <= resize(shift_right(bf_pl(1).B.i * bf_pl(1).TW.i - bf_pl(1).B.q * bf_pl(1).TW.q, BITS-1-POSTBITS), PIPELINE_BITS); + mix.q <= resize(shift_right(bf_pl(1).B.i * bf_pl(1).TW.q + bf_pl(1).B.q * bf_pl(1).TW.i, BITS-1-POSTBITS), PIPELINE_BITS); + T_A.i <= shift_left(bf_pl(2).A.i, POSTBITS) + mix.i; + T_A.q <= shift_left(bf_pl(2).A.q, POSTBITS) + mix.q; + T_B.i <= shift_left(bf_pl(2).A.i, POSTBITS) - mix.i; + T_B.q <= shift_left(bf_pl(2).A.q, POSTBITS) - mix.q; + end if; + end process; + + out_sop <= current.sop; + out_valid <= current.valid; + out_eop <= current.eop; + out_error <= '1' when current.fsm = STOP else '0'; + + out_real <= std_logic_vector(resize(current.out_sample.i, BITS)); + out_imag <= std_logic_vector(resize(current.out_sample.q, BITS)); + + comb : process(all) + variable tmp_addr_a, tmp_addr_b : unsigned(ADDR_BITS-1 downto 0); + variable ones_reg : unsigned(ADDR_BITS-2 downto 0); + variable tmp_tw : complex_sample_t; + begin + tmp_tw := current.tw; + if (inverse = '1' ) then + bf_pl(1).TW <= tmp_tw; + else + bf_pl(1).TW.i <= tmp_tw.i; + bf_pl(1).TW.q <= -tmp_tw.q; + end if; + bf_pl(1).A <= slv_to_cst(curr_data.data_a); + if (current.fsm = FIRST_STAGE or (current.fsm = WAIT_STAGE and current.stage = 0)) then + bf_pl(1).B <= current.N2_sample_r; + else + bf_pl(1).B <= slv_to_cst(curr_data.data_b); + end if; + if (current.buffer_idx = '0') then + muxed_mbc(0) <= current.mbc(0); -- during RUN_STAGES: READ + curr_data <= data_mbc(0); + + muxed_mbc(1) <= comp_mbc; -- during RUN_STAGES: WRITE + else + muxed_mbc(0) <= comp_mbc; -- during RUN_STAGES: WRITE + + muxed_mbc(1) <= current.mbc(0); -- during RUN_STAGES: READ + curr_data <= data_mbc(1); + end if; + + future <= current; + + for i in future.mbc'range loop + future.mbc(i) <= NULL_MEM_BANK_CTRL; + end loop; + future.bf_ready <= '0'; + future.sop <= '0'; + future.eop <= '0'; + future.valid <= '0'; + + ones_reg := ( others => '1' ); + + -- note, this updates on the next cycle + if (current.fsm = FIRST_STAGE or current.fsm = RUN_STAGE or current.fsm = WAIT_STAGE) then + tmp_tw := TLUT(to_integer(current.twiddle_idx)); + future.tw <= tmp_tw; + future.twiddle_idx <= to_unsigned(current.iter, ones_reg'high+1) + and shift_left(ones_reg, NUM_STAGES-1-current.stage); + end if; + + future.N2_sample_r <= current.N2_sample; + + case current.fsm is + when IDLE => + if (in_sop = '1') then + future.fsm <= LOAD; + if (in_valid = '1') then + future.mbc(0).addr_b <= std_logic_vector(to_unsigned(1, ADDR_BITS)); + future.mbc(0).addr_a <= reverse_bit_order(current.write_idx); + future.mbc(0).in_a <= std_logic_vector(resize(signed(in_real), PIPELINE_BITS) & resize(signed(in_imag), PIPELINE_BITS)); + future.mbc(0).acc <= '1'; + future.mbc(0).solo <= '1'; + future.mbc(0).write <= '1'; + future.write_idx <= current.write_idx + 1; + future.count <= 1; + end if; + end if; + when LOAD => + if (in_valid = '1') then + future.write_idx <= current.write_idx + 1; + future.count <= current.count + 1; + if (current.write_idx = (N/2)) then + future.mbc(0).addr_a <= reverse_bit_order(current.write_idx-32); + future.mbc(0).addr_b <= reverse_bit_order(current.write_idx); + future.N2_sample.i <= resize(signed(in_real), PIPELINE_BITS); + future.N2_sample.q <= resize(signed(in_imag), PIPELINE_BITS); + future.bf_ready <= '1'; + future.mbc(0).acc <= '1'; + future.fsm <= FIRST_STAGE; + else + future.mbc(0).addr_b <= std_logic_vector(to_unsigned(1, ADDR_BITS)); + future.mbc(0).addr_a <= reverse_bit_order(current.write_idx); + future.mbc(0).in_a <= std_logic_vector(resize(signed(in_real), PIPELINE_BITS) & resize(signed(in_imag), PIPELINE_BITS)); + future.mbc(0).acc <= '1'; + future.mbc(0).solo <= '1'; + future.mbc(0).write <= '1'; + end if; + end if; + if (in_eop = '1') then + future.fsm <= STOP; + end if; + when FIRST_STAGE => + if (in_valid = '1') then + future.count <= current.count + 1; + future.write_idx <= current.write_idx + 1; + future.bf_ready <= '1'; + future.mbc(0).addr_a <= reverse_bit_order(current.write_idx-32); + future.mbc(0).addr_b <= reverse_bit_order(current.write_idx); + future.mbc(0).acc <= '1'; + future.N2_sample.i <= resize(signed(in_real), PIPELINE_BITS); + future.N2_sample.q <= resize(signed(in_imag), PIPELINE_BITS); + if (current.write_idx = N-1) then + future.iter <= 3; + future.fsm <= WAIT_STAGE; + if (in_eop = '0') then + future.fsm <= STOP; + end if; + else + if (in_eop = '1') then + future.fsm <= STOP; + end if; + end if; + end if; + when RUN_STAGE => + future.mbc(0).acc <= '1'; + future.bf_ready <= '1'; + tmp_addr_a := rotate_left(to_unsigned(current.iter*2, ADDR_BITS), current.stage); + tmp_addr_b := rotate_left(to_unsigned(current.iter*2+1, ADDR_BITS), current.stage); + + future.mbc(0).addr_a <= std_logic_vector(tmp_addr_a); + future.mbc(0).addr_b <= std_logic_vector(tmp_addr_b); + if (current.iter = (N/2)-1) then + future.iter <= 3; + future.fsm <= WAIT_STAGE; + else + future.iter <= current.iter + 1; + end if; + + when WAIT_STAGE => + if (current.iter = 0) then + future.buffer_idx <= not current.buffer_idx; + if (current.stage < NUM_STAGES-1) then + future.stage <= current.stage + 1; + future.fsm <= RUN_STAGE; + future.iter <= 0; + else + future.fsm <= READ_OUT; + future.iter <= N/2 + 2; + future.mbc(0).addr_a <= std_logic_vector(to_unsigned(N/2+1, ADDR_BITS)); + future.mbc(0).acc <= '1'; + future.mbc(0).solo <= '1'; + end if; + else + future.iter <= current.iter - 1; + end if; + when READ_OUT => + if (current.iter = N+1) then + future.fsm <= RESET_STAGE; + future.eop <= '1'; + end if; + if (current.iter < N) then + future.mbc(0).addr_a <= std_logic_vector(to_unsigned(current.iter, ADDR_BITS)); + end if; + future.iter <= current.iter + 1; + future.mbc(0).acc <= '1'; + future.mbc(0).solo <= '1'; + + when others => + future <= NULL_STATE_T; + end case; + + case current.rfsm is + when IDLE => + if (current.fsm = RUN_STAGE and current.stage = NUM_STAGES - 1) then + future.rfsm <= PASSTHROUGH; + end if; + when PASSTHROUGH => + if (current.fsm = RUN_STAGE) then + if (current.iter = 4) then + future.N2_sample <= T_B; + future.sop <= '1'; + end if; + end if; + + if (current.iter > 3 or current.fsm = WAIT_STAGE) then + if (current.iter = (N/2)+2) then + future.out_sample <= shift_sample(current.N2_sample, inverse); + else + future.out_sample <= shift_sample(T_A, inverse); + end if; + future.valid <= '1'; + end if; + + if (current.fsm = READ_OUT) then + future.rfsm <= MEM_READ; + end if; + when MEM_READ => + if (current.iter = N+1) then + future.rfsm <= IDLE; + end if; + future.out_sample <= shift_sample(slv_to_cst(curr_data.data_a), inverse); + future.valid <= '1'; + when others => + future <= NULL_STATE_T; + end case; + + end process; + + +end architecture; diff --git a/testsuite/gna/issue2065/repro.vhdl b/testsuite/gna/issue2065/repro.vhdl new file mode 100644 index 000000000..a6dc56d26 --- /dev/null +++ b/testsuite/gna/issue2065/repro.vhdl @@ -0,0 +1,15 @@ +entity repro is + generic (depth : natural := 5); + port (inp : bit := '0'); +end entity; + +architecture mult of repro is + signal s : bit; +begin + gen: if depth > 0 generate + inst : entity work.repro + generic map (depth => depth - 1) + port map(inp => s and inp); + end generate; +end architecture mult; + diff --git a/testsuite/gna/issue2065/testsuite.sh b/testsuite/gna/issue2065/testsuite.sh new file mode 100755 index 000000000..8cc43fcb1 --- /dev/null +++ b/testsuite/gna/issue2065/testsuite.sh @@ -0,0 +1,14 @@ +#! /bin/sh + +. ../../testenv.sh + +export GHDL_STD_FLAGS=--std=08 +analyze repro.vhdl +elab_simulate repro + +analyze dual_port_ram.vhdl +analyze fft.vhdl + +clean + +echo "Test successful" diff --git a/testsuite/gna/issue2066/aggregate_bug.vhdl b/testsuite/gna/issue2066/aggregate_bug.vhdl new file mode 100644 index 000000000..bf7b53510 --- /dev/null +++ b/testsuite/gna/issue2066/aggregate_bug.vhdl @@ -0,0 +1,18 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity aggregate_bug is +end entity aggregate_bug; + +architecture rtl of aggregate_bug is + signal vec : std_logic_vector(7 downto 0); +begin + vec <= (3 downto 0 => "111", others => '0'); -- Associate a 3 bit element to a 4 bit slice + process + begin + wait for 1 ns; + report to_string(vec); + wait for 1 ns; + std.env.finish; + end process; +end architecture rtl; diff --git a/testsuite/gna/issue2066/repro1.vhdl b/testsuite/gna/issue2066/repro1.vhdl new file mode 100644 index 000000000..aa1dfca11 --- /dev/null +++ b/testsuite/gna/issue2066/repro1.vhdl @@ -0,0 +1,14 @@ +entity repro1 is +end; + +architecture rtl of repro1 is + signal vec : bit_vector(7 downto 0); +begin + vec <= (3 downto 0 => "111", others => '0'); -- Associate a 3 bit element to a 4 bit slice + process + begin + wait for 1 ns; + report to_string(vec); + wait; + end process; +end architecture rtl; diff --git a/testsuite/gna/issue2066/testsuite.sh b/testsuite/gna/issue2066/testsuite.sh new file mode 100755 index 000000000..c763a1451 --- /dev/null +++ b/testsuite/gna/issue2066/testsuite.sh @@ -0,0 +1,14 @@ +#! /bin/sh + +. ../../testenv.sh + +export GHDL_STD_FLAGS=--std=08 +analyze repro1.vhdl +elab_simulate_failure repro1 + +analyze aggregate_bug.vhdl +elab_simulate_failure aggregate_bug + +clean + +echo "Test successful" diff --git a/testsuite/gna/issue2070/crash0.vhdl b/testsuite/gna/issue2070/crash0.vhdl new file mode 100644 index 000000000..e285dfcae --- /dev/null +++ b/testsuite/gna/issue2070/crash0.vhdl @@ -0,0 +1 @@ +%%d%
\ No newline at end of file diff --git a/testsuite/gna/issue2070/crash1.vhdl b/testsuite/gna/issue2070/crash1.vhdl new file mode 100644 index 000000000..f98304df5 --- /dev/null +++ b/testsuite/gna/issue2070/crash1.vhdl @@ -0,0 +1 @@ +d%
\ No newline at end of file diff --git a/testsuite/gna/issue2070/crash10.vhdl b/testsuite/gna/issue2070/crash10.vhdl new file mode 100644 index 000000000..f64680825 --- /dev/null +++ b/testsuite/gna/issue2070/crash10.vhdl @@ -0,0 +1 @@ +D%
\ No newline at end of file diff --git a/testsuite/gna/issue2070/crash11.vhdl b/testsuite/gna/issue2070/crash11.vhdl new file mode 100644 index 000000000..0dd660176 --- /dev/null +++ b/testsuite/gna/issue2070/crash11.vhdl @@ -0,0 +1 @@ +architecture 0for(4000000000x"
\ No newline at end of file diff --git a/testsuite/gna/issue2070/crash12.vhdl b/testsuite/gna/issue2070/crash12.vhdl new file mode 100644 index 000000000..0d0585675 --- /dev/null +++ b/testsuite/gna/issue2070/crash12.vhdl @@ -0,0 +1 @@ +architecture restrict[*9000000000
\ No newline at end of file diff --git a/testsuite/gna/issue2070/crash13.vhdl b/testsuite/gna/issue2070/crash13.vhdl new file mode 100644 index 000000000..4dab5a0e8 --- /dev/null +++ b/testsuite/gna/issue2070/crash13.vhdl @@ -0,0 +1 @@ +architecture¦0for(4000000000x"
\ No newline at end of file diff --git a/testsuite/gna/issue2070/crash14.vhdl b/testsuite/gna/issue2070/crash14.vhdl new file mode 100644 index 000000000..6041db3ea --- /dev/null +++ b/testsuite/gna/issue2070/crash14.vhdl @@ -0,0 +1 @@ +package package
\ No newline at end of file diff --git a/testsuite/gna/issue2070/crash15.vhdl b/testsuite/gna/issue2070/crash15.vhdl new file mode 100644 index 000000000..eda9b99a7 --- /dev/null +++ b/testsuite/gna/issue2070/crash15.vhdl @@ -0,0 +1 @@ +architecture@for(""x""4000000000x"
\ No newline at end of file diff --git a/testsuite/gna/issue2070/crash16.vhdl b/testsuite/gna/issue2070/crash16.vhdl new file mode 100644 index 000000000..5d99067f3 --- /dev/null +++ b/testsuite/gna/issue2070/crash16.vhdl @@ -0,0 +1 @@ +architecture 0for(""x""4000000000x"
\ No newline at end of file diff --git a/testsuite/gna/issue2070/crash17.vhdl b/testsuite/gna/issue2070/crash17.vhdl new file mode 100644 index 000000000..1ce62ef37 --- /dev/null +++ b/testsuite/gna/issue2070/crash17.vhdl @@ -0,0 +1,2 @@ +architecture function is +0package
\ No newline at end of file diff --git a/testsuite/gna/issue2070/crash18.vhdl b/testsuite/gna/issue2070/crash18.vhdl new file mode 100644 index 000000000..a0dd4f571 --- /dev/null +++ b/testsuite/gna/issue2070/crash18.vhdl @@ -0,0 +1 @@ +architecture function is;0package
\ No newline at end of file diff --git a/testsuite/gna/issue2070/crash19.vhdl b/testsuite/gna/issue2070/crash19.vhdl new file mode 100644 index 000000000..65009429e --- /dev/null +++ b/testsuite/gna/issue2070/crash19.vhdl @@ -0,0 +1 @@ +architecture package
\ No newline at end of file diff --git a/testsuite/gna/issue2070/crash2.vhdl b/testsuite/gna/issue2070/crash2.vhdl new file mode 100644 index 000000000..203877edb --- /dev/null +++ b/testsuite/gna/issue2070/crash2.vhdl @@ -0,0 +1 @@ +architecture if''h';
\ No newline at end of file diff --git a/testsuite/gna/issue2070/crash20.vhdl b/testsuite/gna/issue2070/crash20.vhdl new file mode 100644 index 000000000..d637382eb --- /dev/null +++ b/testsuite/gna/issue2070/crash20.vhdl @@ -0,0 +1,3 @@ +package-- +function is +if)h';
\ No newline at end of file diff --git a/testsuite/gna/issue2070/crash21.vhdl b/testsuite/gna/issue2070/crash21.vhdl new file mode 100644 index 000000000..18fe7e00c --- /dev/null +++ b/testsuite/gna/issue2070/crash21.vhdl @@ -0,0 +1 @@ +architecture;b';
\ No newline at end of file diff --git a/testsuite/gna/issue2070/crash22.vhdl b/testsuite/gna/issue2070/crash22.vhdl new file mode 100644 index 000000000..83b140f4c --- /dev/null +++ b/testsuite/gna/issue2070/crash22.vhdl @@ -0,0 +1 @@ +architecture if''h';
\ No newline at end of file diff --git a/testsuite/gna/issue2070/crash23.vhdl b/testsuite/gna/issue2070/crash23.vhdl new file mode 100644 index 000000000..0570a5eb5 --- /dev/null +++ b/testsuite/gna/issue2070/crash23.vhdl @@ -0,0 +1,2 @@ +context is +library use T.context is
\ No newline at end of file diff --git a/testsuite/gna/issue2070/crash23_1.vhdl b/testsuite/gna/issue2070/crash23_1.vhdl new file mode 100644 index 000000000..8e086380f --- /dev/null +++ b/testsuite/gna/issue2070/crash23_1.vhdl @@ -0,0 +1,5 @@ +context a is + library ieee; + context b is + end; +end; diff --git a/testsuite/gna/issue2070/crash24.vhdl b/testsuite/gna/issue2070/crash24.vhdl Binary files differnew file mode 100644 index 000000000..4936b8e12 --- /dev/null +++ b/testsuite/gna/issue2070/crash24.vhdl diff --git a/testsuite/gna/issue2070/crash25.vhdl b/testsuite/gna/issue2070/crash25.vhdl new file mode 100644 index 000000000..4a48fd280 --- /dev/null +++ b/testsuite/gna/issue2070/crash25.vhdl @@ -0,0 +1,2 @@ +package-- +function is;n';
\ No newline at end of file diff --git a/testsuite/gna/issue2070/crash26.vhdl b/testsuite/gna/issue2070/crash26.vhdl new file mode 100644 index 000000000..44271032d --- /dev/null +++ b/testsuite/gna/issue2070/crash26.vhdl @@ -0,0 +1 @@ +entity package
\ No newline at end of file diff --git a/testsuite/gna/issue2070/crash27.vhdl b/testsuite/gna/issue2070/crash27.vhdl new file mode 100644 index 000000000..328403293 --- /dev/null +++ b/testsuite/gna/issue2070/crash27.vhdl @@ -0,0 +1 @@ +architecture if''e';
\ No newline at end of file diff --git a/testsuite/gna/issue2070/crash28.vhdl b/testsuite/gna/issue2070/crash28.vhdl new file mode 100644 index 000000000..adb997110 --- /dev/null +++ b/testsuite/gna/issue2070/crash28.vhdl @@ -0,0 +1 @@ +package body function begin 0package
\ No newline at end of file diff --git a/testsuite/gna/issue2070/crash29.vhdl b/testsuite/gna/issue2070/crash29.vhdl new file mode 100644 index 000000000..01bb9535a --- /dev/null +++ b/testsuite/gna/issue2070/crash29.vhdl @@ -0,0 +1,5 @@ +package n is +function t return n;end;package body n is +function get return l is begin end get;end;package n is generic(package g is new w generic map(<>));function t return l;end;package body gen0 is use p;function g return l is begin end;end gen0;package b is +end;architecture beha0 of b is +begin end beha0;
\ No newline at end of file diff --git a/testsuite/gna/issue2070/crash29_1.vhdl b/testsuite/gna/issue2070/crash29_1.vhdl new file mode 100644 index 000000000..d6a4037ae --- /dev/null +++ b/testsuite/gna/issue2070/crash29_1.vhdl @@ -0,0 +1,4 @@ +package n is + generic(package g is new w generic map(<>)); + function t return l; +end; diff --git a/testsuite/gna/issue2070/crash29_2.vhdl b/testsuite/gna/issue2070/crash29_2.vhdl new file mode 100644 index 000000000..1c9a979bb --- /dev/null +++ b/testsuite/gna/issue2070/crash29_2.vhdl @@ -0,0 +1,27 @@ +package n is + function t return n; +end; +package body n is + function get return l is + begin + end get; +end; + +package n is + generic(package g is new w generic map(<>)); + function t return l; +end; + +package body gen0 is + use p; + function g return l is + begin + end; +end gen0; + +package b is +end; + +architecture beha0 of b is +begin +end beha0; diff --git a/testsuite/gna/issue2070/crash3.vhdl b/testsuite/gna/issue2070/crash3.vhdl new file mode 100644 index 000000000..7b0125363 --- /dev/null +++ b/testsuite/gna/issue2070/crash3.vhdl @@ -0,0 +1 @@ +architecture;l';
\ No newline at end of file diff --git a/testsuite/gna/issue2070/crash30.vhdl b/testsuite/gna/issue2070/crash30.vhdl new file mode 100644 index 000000000..83513ef29 --- /dev/null +++ b/testsuite/gna/issue2070/crash30.vhdl @@ -0,0 +1,4 @@ +package n is +function t return n;end;package d is +end;package gen0 is generic(package g is new w generic map(<>));function t return l;end gen0;package body gen0 is use p;function g return l;end gen0;package g is new n;package p is new w generic map(0);architecture beha0 of b is +begin end beha0;
\ No newline at end of file diff --git a/testsuite/gna/issue2070/crash31.vhdl b/testsuite/gna/issue2070/crash31.vhdl new file mode 100644 index 000000000..801339647 --- /dev/null +++ b/testsuite/gna/issue2070/crash31.vhdl @@ -0,0 +1 @@ +package function return of
\ No newline at end of file diff --git a/testsuite/gna/issue2070/crash32.vhdl b/testsuite/gna/issue2070/crash32.vhdl new file mode 100644 index 000000000..3c7743bda --- /dev/null +++ b/testsuite/gna/issue2070/crash32.vhdl @@ -0,0 +1 @@ +package function is;s';
\ No newline at end of file diff --git a/testsuite/gna/issue2070/crash33.vhdl b/testsuite/gna/issue2070/crash33.vhdl new file mode 100644 index 000000000..020a0bedf --- /dev/null +++ b/testsuite/gna/issue2070/crash33.vhdl @@ -0,0 +1 @@ +package function(0is if XŠX';
\ No newline at end of file diff --git a/testsuite/gna/issue2070/crash34.vhdl b/testsuite/gna/issue2070/crash34.vhdl new file mode 100644 index 000000000..8d1c7b6e2 --- /dev/null +++ b/testsuite/gna/issue2070/crash34.vhdl @@ -0,0 +1,2 @@ +package function is loop +t((:';
\ No newline at end of file diff --git a/testsuite/gna/issue2070/crash35.vhdl b/testsuite/gna/issue2070/crash35.vhdl new file mode 100644 index 000000000..2c3217103 --- /dev/null +++ b/testsuite/gna/issue2070/crash35.vhdl @@ -0,0 +1 @@ +package function is;i';
\ No newline at end of file diff --git a/testsuite/gna/issue2070/crash36.vhdl b/testsuite/gna/issue2070/crash36.vhdl new file mode 100644 index 000000000..04c0f238c --- /dev/null +++ b/testsuite/gna/issue2070/crash36.vhdl @@ -0,0 +1 @@ +package function is;X';
\ No newline at end of file diff --git a/testsuite/gna/issue2070/crash37.vhdl b/testsuite/gna/issue2070/crash37.vhdl new file mode 100644 index 000000000..0708694da --- /dev/null +++ b/testsuite/gna/issue2070/crash37.vhdl @@ -0,0 +1,2 @@ +package function is +if)n';
\ No newline at end of file diff --git a/testsuite/gna/issue2070/crash38.vhdl b/testsuite/gna/issue2070/crash38.vhdl new file mode 100644 index 000000000..221e8bbd5 --- /dev/null +++ b/testsuite/gna/issue2070/crash38.vhdl @@ -0,0 +1,5 @@ +library IEEE;use IEEE.numeric_std.all;entity tb is +end;architecture behavioral of tb is +subtype int31 is integer range-0*(0)to 2**(31);type a is array(0)of i;function A(v:l)return r is variable s:d(0);begin r((0));end;begin +process +variable t:t;variable tmp:int31;begin tmp:=0;end process;end behavioral;
\ No newline at end of file diff --git a/testsuite/gna/issue2070/crash38_1.vhdl b/testsuite/gna/issue2070/crash38_1.vhdl new file mode 100644 index 000000000..2b44e0aec --- /dev/null +++ b/testsuite/gna/issue2070/crash38_1.vhdl @@ -0,0 +1,14 @@ +library IEEE;use IEEE.numeric_std.all; + +entity tb is +end; + +architecture behavioral of tb is + subtype int31 is integer range-0*(0)to 2**(31); +begin + process + variable tmp:int31; + begin + tmp:=0; + end process; +end behavioral; diff --git a/testsuite/gna/issue2070/crash39.vhdl b/testsuite/gna/issue2070/crash39.vhdl new file mode 100644 index 000000000..f91696171 --- /dev/null +++ b/testsuite/gna/issue2070/crash39.vhdl @@ -0,0 +1,2 @@ +package-- +function is if('t ÿ';
\ No newline at end of file diff --git a/testsuite/gna/issue2070/crash4.vhdl b/testsuite/gna/issue2070/crash4.vhdl new file mode 100644 index 000000000..5b76923d8 --- /dev/null +++ b/testsuite/gna/issue2070/crash4.vhdl @@ -0,0 +1,2 @@ +package-- +function(0is;r';
\ No newline at end of file diff --git a/testsuite/gna/issue2070/crash40.vhdl b/testsuite/gna/issue2070/crash40.vhdl new file mode 100644 index 000000000..8539ad734 --- /dev/null +++ b/testsuite/gna/issue2070/crash40.vhdl @@ -0,0 +1 @@ +architecture function(0is;0package
\ No newline at end of file diff --git a/testsuite/gna/issue2070/crash41.vhdl b/testsuite/gna/issue2070/crash41.vhdl new file mode 100644 index 000000000..fa2399a01 --- /dev/null +++ b/testsuite/gna/issue2070/crash41.vhdl @@ -0,0 +1,3 @@ +package function-- +begin +X';
\ No newline at end of file diff --git a/testsuite/gna/issue2070/crash42.vhdl b/testsuite/gna/issue2070/crash42.vhdl new file mode 100644 index 000000000..116afbcc1 --- /dev/null +++ b/testsuite/gna/issue2070/crash42.vhdl @@ -0,0 +1,2 @@ +package +function begin if a s';
\ No newline at end of file diff --git a/testsuite/gna/issue2070/crash43.vhdl b/testsuite/gna/issue2070/crash43.vhdl new file mode 100644 index 000000000..d9b94dca4 --- /dev/null +++ b/testsuite/gna/issue2070/crash43.vhdl @@ -0,0 +1,2 @@ +package +function begin if a r';
\ No newline at end of file diff --git a/testsuite/gna/issue2070/crash44.vhdl b/testsuite/gna/issue2070/crash44.vhdl new file mode 100644 index 000000000..20a06b633 --- /dev/null +++ b/testsuite/gna/issue2070/crash44.vhdl @@ -0,0 +1 @@ +package function""begin r';
\ No newline at end of file diff --git a/testsuite/gna/issue2070/crash45.vhdl b/testsuite/gna/issue2070/crash45.vhdl new file mode 100644 index 000000000..714919de4 --- /dev/null +++ b/testsuite/gna/issue2070/crash45.vhdl @@ -0,0 +1,7 @@ +library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std;entity full_adder_tb is +end entity full_adder_tb;architecture sim of full_adder_tb is +type rc_data is record +a:c;n:c;s:s;t:std_logic;end record;type fa_array is array(0 range<>)of rc_data;constant e:fa_array:=(('0','0','0','%'),('0'));begin +process +begin +end process;D(0);end architecture sim;
\ No newline at end of file diff --git a/testsuite/gna/issue2070/crash45_1.vhdl b/testsuite/gna/issue2070/crash45_1.vhdl new file mode 100644 index 000000000..9f5c54070 --- /dev/null +++ b/testsuite/gna/issue2070/crash45_1.vhdl @@ -0,0 +1,14 @@ +library ieee;use ieee.std_logic_1164.all; +use ieee.numeric_std; + +entity full_adder_tb is +end entity full_adder_tb; + +architecture sim of full_adder_tb is + type rc_data is record + a : character; + t:std_logic; + end record; + constant e:rc_data:=('0','%'); +begin +end architecture sim; diff --git a/testsuite/gna/issue2070/crash46.vhdl b/testsuite/gna/issue2070/crash46.vhdl new file mode 100644 index 000000000..c7d39a38a --- /dev/null +++ b/testsuite/gna/issue2070/crash46.vhdl @@ -0,0 +1,2 @@ +context is +context is
\ No newline at end of file diff --git a/testsuite/gna/issue2070/crash47.vhdl b/testsuite/gna/issue2070/crash47.vhdl new file mode 100644 index 000000000..948e9a24d --- /dev/null +++ b/testsuite/gna/issue2070/crash47.vhdl @@ -0,0 +1,3 @@ +entity g is generic(type stream0t);port(t:t stream0t);end;architecture t of g is type e is array(0)of m;signal w:r range 0 to 0;signal r:r range 0 to 0;signal m:n;begin +y(0);process(a)begin if(0)then +if 0 then(0)<=0;end if;end if;end process;end;
\ No newline at end of file diff --git a/testsuite/gna/issue2070/crash47_1.vhdl b/testsuite/gna/issue2070/crash47_1.vhdl new file mode 100644 index 000000000..34f9eee95 --- /dev/null +++ b/testsuite/gna/issue2070/crash47_1.vhdl @@ -0,0 +1,20 @@ +entity g is + generic(type stream0t); + port(t:t stream0t); +end; + +architecture t of g is + type e is array(0)of m; + signal w:r range 0 to 0; + signal r:r range 0 to 0; + signal m:n; +begin + y(0); + process(a) + begin + if(0)then + if 0 then(0)<=0; + end if; + end if; + end process; +end; diff --git a/testsuite/gna/issue2070/crash48.vhdl b/testsuite/gna/issue2070/crash48.vhdl new file mode 100644 index 000000000..97b0d7f23 --- /dev/null +++ b/testsuite/gna/issue2070/crash48.vhdl @@ -0,0 +1,6 @@ +package float0generic0pkg is generic(package g is new I generic map(<>));-- +function a(l:t;-- +e:N:=0)-- +return t;function m(r:e)return t;-- +function t(g:d;-- +h:h)return t;function p(s:t)return t;alias m is m;function r(e:t)return t;alias f is m;end float0generic0pkg;
\ No newline at end of file diff --git a/testsuite/gna/issue2070/crash49.vhdl b/testsuite/gna/issue2070/crash49.vhdl new file mode 100644 index 000000000..705406049 --- /dev/null +++ b/testsuite/gna/issue2070/crash49.vhdl @@ -0,0 +1,5 @@ +library IEEE;use IEEE.numeric_std.all;entity tb is +end;architecture behavioral of tb is +subtype int01 is integer range-0**(-1)to(0);type a is array(0)of i;function A(v:l)return r is variable p:d(0);begin e(0)(0);r((0));end;begin +process +variable t:t;variable tmp:int01;begin tmp:=0;end process;end behavioral;
\ No newline at end of file diff --git a/testsuite/gna/issue2070/crash5.vhdl b/testsuite/gna/issue2070/crash5.vhdl new file mode 100644 index 000000000..0859877b7 --- /dev/null +++ b/testsuite/gna/issue2070/crash5.vhdl @@ -0,0 +1,2 @@ +package function begin-- +n';
\ No newline at end of file diff --git a/testsuite/gna/issue2070/crash50.vhdl b/testsuite/gna/issue2070/crash50.vhdl new file mode 100644 index 000000000..197f29ebc --- /dev/null +++ b/testsuite/gna/issue2070/crash50.vhdl @@ -0,0 +1,2 @@ +package function begin-- +ÿ';
\ No newline at end of file diff --git a/testsuite/gna/issue2070/crash51.vhdl b/testsuite/gna/issue2070/crash51.vhdl new file mode 100644 index 000000000..8512bfa02 --- /dev/null +++ b/testsuite/gna/issue2070/crash51.vhdl @@ -0,0 +1 @@ +architecture;s';
\ No newline at end of file diff --git a/testsuite/gna/issue2070/crash52.vhdl b/testsuite/gna/issue2070/crash52.vhdl new file mode 100644 index 000000000..b91dbafb1 --- /dev/null +++ b/testsuite/gna/issue2070/crash52.vhdl @@ -0,0 +1,5 @@ +library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;entity full_adder_tb is +end entity full_adder_tb;architecture sim of full_adder_tb is-- +type rc_data is record a:c;c:std_logic;end record rc_data;type fa_array is array(0)of rc_data;constant f:fa_array:=(('0'),('0','%'),('0'));begin process begin +for i in 0 loop +end loop;end process;p(0);end architecture sim;
\ No newline at end of file diff --git a/testsuite/gna/issue2070/crash53.vhdl b/testsuite/gna/issue2070/crash53.vhdl new file mode 100644 index 000000000..e8f3de699 --- /dev/null +++ b/testsuite/gna/issue2070/crash53.vhdl @@ -0,0 +1,7 @@ +library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;entity full_adder_tb is +end entity full_adder_tb;architecture m of full_adder_tb is-- +type rc_data is record n:c;t:std_logic;end record rc_data;type fa_array is array(0 range<>)of rc_data;constant e:fa_array:=(('0'),('0','%','0'),('0'));begin +process +begin +for i in 0 loop +end loop;end process;p(0);end;
\ No newline at end of file diff --git a/testsuite/gna/issue2070/crash54.vhdl b/testsuite/gna/issue2070/crash54.vhdl new file mode 100644 index 000000000..fcadd4fa0 --- /dev/null +++ b/testsuite/gna/issue2070/crash54.vhdl @@ -0,0 +1,5 @@ +library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;entity full_adder_tb is +end entity full_adder_tb;architecture m of full_adder_tb is-- +type rc_data is record a:c;c:std_logic;end record rc_data;type fa_array is array(0)of rc_data;constant f:fa_array:=(('0'),('0','%'));begin process begin +for i in 0 loop +end loop;end process;r(0);end architecture;
\ No newline at end of file diff --git a/testsuite/gna/issue2070/crash55.vhdl b/testsuite/gna/issue2070/crash55.vhdl new file mode 100644 index 000000000..e261f5a9c --- /dev/null +++ b/testsuite/gna/issue2070/crash55.vhdl @@ -0,0 +1,2 @@ +CONTEXT is +context is
\ No newline at end of file diff --git a/testsuite/gna/issue2070/crash6.vhdl b/testsuite/gna/issue2070/crash6.vhdl new file mode 100644 index 000000000..fbc216a49 --- /dev/null +++ b/testsuite/gna/issue2070/crash6.vhdl @@ -0,0 +1,3 @@ +package-- +function(0is +while()0X';
\ No newline at end of file diff --git a/testsuite/gna/issue2070/crash7.vhdl b/testsuite/gna/issue2070/crash7.vhdl new file mode 100644 index 000000000..e2e603191 --- /dev/null +++ b/testsuite/gna/issue2070/crash7.vhdl @@ -0,0 +1 @@ +package function begin if t X';
\ No newline at end of file diff --git a/testsuite/gna/issue2070/crash8.vhdl b/testsuite/gna/issue2070/crash8.vhdl new file mode 100644 index 000000000..fbdf3cdff --- /dev/null +++ b/testsuite/gna/issue2070/crash8.vhdl @@ -0,0 +1 @@ +package function begin c';
\ No newline at end of file diff --git a/testsuite/gna/issue2070/crash9.vhdl b/testsuite/gna/issue2070/crash9.vhdl new file mode 100644 index 000000000..fead40f2a --- /dev/null +++ b/testsuite/gna/issue2070/crash9.vhdl @@ -0,0 +1,2 @@ +package function begin-- +X';
\ No newline at end of file diff --git a/testsuite/gna/issue2070/testsuite.sh b/testsuite/gna/issue2070/testsuite.sh new file mode 100755 index 000000000..ec0fac15f --- /dev/null +++ b/testsuite/gna/issue2070/testsuite.sh @@ -0,0 +1,71 @@ +#! /bin/sh + +. ../../testenv.sh + +files=" +crash0.vhdl +crash1.vhdl +crash10.vhdl +crash11.vhdl +crash12.vhdl +crash13.vhdl +crash14.vhdl +crash15.vhdl +crash16.vhdl +crash17.vhdl +crash18.vhdl +crash19.vhdl +crash2.vhdl +crash20.vhdl +crash21.vhdl +crash22.vhdl +crash23.vhdl +crash24.vhdl +crash25.vhdl +crash26.vhdl +crash27.vhdl +crash28.vhdl +crash29.vhdl +crash3.vhdl +crash30.vhdl +crash31.vhdl +crash32.vhdl +crash33.vhdl +crash34.vhdl +crash35.vhdl +crash36.vhdl +crash37.vhdl +crash38.vhdl +crash39.vhdl +crash4.vhdl +crash40.vhdl +crash41.vhdl +crash42.vhdl +crash43.vhdl +crash44.vhdl +crash45.vhdl +crash46.vhdl +crash47.vhdl +crash48.vhdl +crash49.vhdl +crash5.vhdl +crash50.vhdl +crash51.vhdl +crash52.vhdl +crash53.vhdl +crash54.vhdl +crash55.vhdl +crash6.vhdl +crash7.vhdl +crash8.vhdl +crash9.vhdl +" + +export GHDL_STD_FLAGS=--std=08 +for f in $files; do + analyze_failure $f +done + +clean + +echo "Test successful" diff --git a/testsuite/gna/issue2071/repro.vhdl b/testsuite/gna/issue2071/repro.vhdl new file mode 100644 index 000000000..aa6bcf1c0 --- /dev/null +++ b/testsuite/gna/issue2071/repro.vhdl @@ -0,0 +1,18 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity repro is +end; + +architecture behav of repro is + type matrixType is array(natural range <>) of std_logic_vector; + signal matrix : matrixType(0 to 15)(7 downto 0); + + -- Missing feature: + signal row1 : unsigned(matrix'element'range); + + -- As a workaround: + signal row2 : unsigned(matrix(matrix'low)'range); +begin +end behav; diff --git a/testsuite/gna/issue2071/repro2.vhdl b/testsuite/gna/issue2071/repro2.vhdl new file mode 100644 index 000000000..f00671310 --- /dev/null +++ b/testsuite/gna/issue2071/repro2.vhdl @@ -0,0 +1,37 @@ +package TST_PKG is + type Indices_t is array (natural range <>) of bit_vector; + + type Bus_t is record + Indices : Indices_t; + end record; + + function Init( + TST_PKG_bus : Bus_t + ) return Bus_t; + +end package; + +package body TST_PKG is + function Init( + TST_PKG_bus : Bus_t + ) + return Bus_t is + variable result : Bus_t( + Indices(TST_PKG_bus.Indices'range)(TST_PKG_bus.Indices'element'range) + ); + begin + result.Indices := (others => (others => '0')); + return result; + end function Init; +end package body; + +use work.tst_pkg.all; + +entity repro2 is +end; + +architecture arch of repro2 is + constant c1 : bus_t := (indices => (1 to 4 => "01")); + constant c2 : bus_t := init (c1); +begin +end; diff --git a/testsuite/gna/issue2071/testsuite.sh b/testsuite/gna/issue2071/testsuite.sh new file mode 100755 index 000000000..b48031476 --- /dev/null +++ b/testsuite/gna/issue2071/testsuite.sh @@ -0,0 +1,14 @@ +#! /bin/sh + +. ../../testenv.sh + +export GHDL_STD_FLAGS=--std=08 +analyze repro.vhdl +elab_simulate repro + +analyze tst.vhdl +elab_simulate tst + +clean + +echo "Test successful" diff --git a/testsuite/gna/issue2071/tst.vhdl b/testsuite/gna/issue2071/tst.vhdl new file mode 100644 index 000000000..a8eb2c94d --- /dev/null +++ b/testsuite/gna/issue2071/tst.vhdl @@ -0,0 +1,42 @@ +library ieee; +use ieee.std_logic_1164.all; + +package TST_PKG is + type Indices_t is array (natural range <>) of std_logic_vector; + + type Bus_t is record + Indices : Indices_t; + end record; + + function Init( + TST_PKG_bus : Bus_t + ) return Bus_t; + +end package; + +package body TST_PKG is + function Init( + TST_PKG_bus : Bus_t + ) + return Bus_t is + variable result : Bus_t( + Indices(TST_PKG_bus.Indices'range)(TST_PKG_bus.Indices'element'range) + ); + begin + result.Indices := (others => (others => '0')); + return result; + end function Init; +end package body; + +library ieee; +use ieee.std_logic_1164.all; +use work.tst_pkg.all; + +entity tst is +end; + +architecture arch of tst is + constant c1 : bus_t := (indices => (1 to 4 => "01")); + constant c2 : bus_t := init (c1); +begin +end; diff --git a/testsuite/gna/issue2076/gcrash-1a.vhdl b/testsuite/gna/issue2076/gcrash-1a.vhdl new file mode 100644 index 000000000..6b56a7be1 --- /dev/null +++ b/testsuite/gna/issue2076/gcrash-1a.vhdl @@ -0,0 +1,5 @@ +package pkg2 is + generic ( + function func (a: integer) return natupac of integer + ); +end pkg2; diff --git a/testsuite/gna/issue2076/gcrash-6a.vhdl b/testsuite/gna/issue2076/gcrash-6a.vhdl new file mode 100644 index 000000000..f29b9ba36 --- /dev/null +++ b/testsuite/gna/issue2076/gcrash-6a.vhdl @@ -0,0 +1,12 @@ +entity full_adder_tb is +end entity full_adder_tb; + +architecture sim of full_adder_tb is +begin + + process + begin + stx.env(i).b; + wait; + end process; +end architecture sim; diff --git a/testsuite/gna/issue2076/gcrash-9a.vhdl b/testsuite/gna/issue2076/gcrash-9a.vhdl new file mode 100644 index 000000000..9ce2175c6 --- /dev/null +++ b/testsuite/gna/issue2076/gcrash-9a.vhdl @@ -0,0 +1,4 @@ +package g0 is + package is + end package; +end package; diff --git a/testsuite/gna/issue2076/testsuite.sh b/testsuite/gna/issue2076/testsuite.sh new file mode 100755 index 000000000..82a824f43 --- /dev/null +++ b/testsuite/gna/issue2076/testsuite.sh @@ -0,0 +1,18 @@ +#! /bin/sh + +. ../../testenv.sh + +files=" +gcrash-1a.vhdl +gcrash-6a.vhdl +gcrash-9a.vhdl +" + +export GHDL_STD_FLAGS=--std=08 +for f in $files; do + analyze_failure $f +done + +clean + +echo "Test successful" diff --git a/testsuite/gna/issue2091/log.vhdl b/testsuite/gna/issue2091/log.vhdl new file mode 100644 index 000000000..265ce412b --- /dev/null +++ b/testsuite/gna/issue2091/log.vhdl @@ -0,0 +1,79 @@ +library std; + use std.textio.all; + +package log is + + type t_level is (TRACE, DEBUG, INFO, WARN, ERROR); + + type t_logger is protected + procedure set_level(lvl : t_level); + + procedure trace(msg : string); + procedure debug(msg : string); + procedure info(msg : string); + procedure warn(msg : string); + procedure error(msg : string); + end protected; + + shared variable logger : t_logger; + + procedure trace(msg : string); + procedure debug(msg : string); + procedure info(msg : string); + procedure warn(msg : string); + procedure error(msg : string); + +end package; + +package body log is + + procedure trace(msg : string) is begin logger.trace(msg); end procedure; + procedure debug(msg : string) is begin logger.debug(msg); end procedure; + procedure info(msg : string) is begin logger.info(msg); end procedure; + procedure warn(msg : string) is begin logger.warn(msg); end procedure; + procedure error(msg : string) is begin logger.error(msg); end procedure; + + type t_logger is protected body + variable level : t_level := INFO; + variable show_level : boolean := true; + + variable time_unit : time := ns; + variable show_sim_time : boolean := true; + + procedure set_level(lvl : t_level) is + begin + level := lvl; + end procedure; + + procedure log(lvl : t_level; msg : string) is + constant MAX_TIME_LEN : positive := 32; + variable time : string(1 to MAX_TIME_LEN); + variable time_line : line; + + procedure trim_time(t : inout string) is + begin + for i in t'reverse_range loop + if t(i) = ' ' then time(i) := nul; else return; end if; + end loop; + end procedure; + begin + if lvl < level then return; end if; + + if show_sim_time then + write(time_line, now, left, MAX_TIME_LEN, time_unit); + time := time_line.all; + trim_time(time); + end if; + + write(output, t_level'image(lvl) & ": " & time & ": " & msg & LF); + end procedure; + + procedure trace(msg : string) is begin log(TRACE, msg); end procedure; + procedure debug(msg : string) is begin log(DEBUG, msg); end procedure; + procedure info(msg : string) is begin log(INFO, msg); end procedure; + procedure warn(msg : string) is begin log(WARN, msg); end procedure; + procedure error(msg : string) is begin log(ERROR, msg); end procedure; + + end protected body; + +end package body; diff --git a/testsuite/gna/issue2091/test.vhdl b/testsuite/gna/issue2091/test.vhdl new file mode 100644 index 000000000..99c13af52 --- /dev/null +++ b/testsuite/gna/issue2091/test.vhdl @@ -0,0 +1,27 @@ +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library work; + use work.log; + +entity test is +end entity; + +architecture tb of test is +begin + main : process is + begin + wait for 7.5 ns; + + log.logger.set_level(log.TRACE); + + log.trace("TRACE"); + log.debug("DEBUG"); + log.info("INFO"); + log.warn("WARN"); + log.error("ERROR"); + + std.env.finish; + end process; +end architecture; diff --git a/testsuite/gna/issue2091/testsuite.sh b/testsuite/gna/issue2091/testsuite.sh new file mode 100755 index 000000000..17151b5d2 --- /dev/null +++ b/testsuite/gna/issue2091/testsuite.sh @@ -0,0 +1,11 @@ +#! /bin/sh + +. ../../testenv.sh + +export GHDL_STD_FLAGS=--std=08 +analyze log.vhdl test.vhdl +elab_simulate test + +clean + +echo "Test successful" diff --git a/testsuite/gna/issue2097/my_fixed_pkg.vhdl b/testsuite/gna/issue2097/my_fixed_pkg.vhdl new file mode 100644 index 000000000..eee9cde50 --- /dev/null +++ b/testsuite/gna/issue2097/my_fixed_pkg.vhdl @@ -0,0 +1,7 @@ +library IEEE; +context IEEE.IEEE_std_context; + +package my_fixed_pkg is new IEEE.fixed_generic_pkg; + +--! + diff --git a/testsuite/gna/issue2097/tb_fixed.vhdl b/testsuite/gna/issue2097/tb_fixed.vhdl new file mode 100644 index 000000000..658026dae --- /dev/null +++ b/testsuite/gna/issue2097/tb_fixed.vhdl @@ -0,0 +1,55 @@ +library IEEE; +context IEEE.IEEE_std_context; + +package my_fixed_pkg is new IEEE.fixed_generic_pkg; + +--! + +library IEEE; +context IEEE.IEEE_std_context; + +library work; +use work.my_fixed_pkg.all; + +entity tb_fixed is +end; + +architecture arch of tb_fixed is + +begin + + process + constant ref : real := -9.96484375; + + subtype stype is sfixed(7 downto -8); + + -- Subtype not allowed as size_res argument of to_sfixed: + -- constant input : std_logic_vector (stype'length-1 downto 0) := to_slv(to_sfixed(ref, stype)); + -- Therefore, a variable needs to be created: + variable fmt : stype; + constant input : std_logic_vector (stype'length-1 downto 0) := to_slv(to_sfixed(ref, fmt)); + + variable sfmt : fmt'subtype; + + procedure report_sfixed(arg: sfixed) is begin report to_string(to_real(arg)); end procedure; + + begin + report_sfixed(stype(input)); + report_sfixed(stype(signed(input))); + + -- CRASH + report_sfixed(fmt'subtype(input)); + -- CRASH + report_sfixed(fmt'subtype(signed(input))); + + -- CRASH + report to_string(fmt'subtype); + + -- However, sfmt, which is declared using fmt'subtype, does work + sfmt := stype(input); + report_sfixed(sfmt); + + wait; + end process; + +end; diff --git a/testsuite/gna/issue2097/tb_fixed1.vhdl b/testsuite/gna/issue2097/tb_fixed1.vhdl new file mode 100644 index 000000000..1a2d02c6f --- /dev/null +++ b/testsuite/gna/issue2097/tb_fixed1.vhdl @@ -0,0 +1,43 @@ +library IEEE; +context IEEE.IEEE_std_context; + +library work; +use work.my_fixed_pkg.all; + +entity tb_fixed1 is +end; + +architecture arch of tb_fixed1 is + +begin + + process + constant ref : real := -9.96484375; + + subtype stype is sfixed(7 downto -8); + + -- Subtype not allowed as size_res argument of to_sfixed: + -- constant input : std_logic_vector (stype'length-1 downto 0) := to_slv(to_sfixed(ref, stype)); + -- Therefore, a variable needs to be created: + variable fmt : stype; + constant input : std_logic_vector (stype'length-1 downto 0) := to_slv(to_sfixed(ref, fmt)); + + variable sfmt : fmt'subtype; + + procedure report_sfixed(arg: sfixed) is begin report to_string(to_real(arg)); end procedure; + + begin + report_sfixed(stype(input)); + report_sfixed(stype(signed(input))); + + -- CRASH + report_sfixed(fmt'subtype(input)); + + -- However, sfmt, which is declared using fmt'subtype, does work + sfmt := stype(input); + report_sfixed(sfmt); + + wait; + end process; + +end; diff --git a/testsuite/gna/issue2097/tb_fixed2.vhdl b/testsuite/gna/issue2097/tb_fixed2.vhdl new file mode 100644 index 000000000..777718f21 --- /dev/null +++ b/testsuite/gna/issue2097/tb_fixed2.vhdl @@ -0,0 +1,43 @@ +library IEEE; +context IEEE.IEEE_std_context; + +library work; +use work.my_fixed_pkg.all; + +entity tb_fixed2 is +end; + +architecture arch of tb_fixed2 is + +begin + + process + constant ref : real := -9.96484375; + + subtype stype is sfixed(7 downto -8); + + -- Subtype not allowed as size_res argument of to_sfixed: + -- constant input : std_logic_vector (stype'length-1 downto 0) := to_slv(to_sfixed(ref, stype)); + -- Therefore, a variable needs to be created: + variable fmt : stype; + constant input : std_logic_vector (stype'length-1 downto 0) := to_slv(to_sfixed(ref, fmt)); + + variable sfmt : fmt'subtype; + + procedure report_sfixed(arg: sfixed) is begin report to_string(to_real(arg)); end procedure; + + begin + report_sfixed(stype(input)); + report_sfixed(stype(signed(input))); + + -- CRASH + report_sfixed(fmt'subtype(signed(input))); + + -- However, sfmt, which is declared using fmt'subtype, does work + sfmt := stype(input); + report_sfixed(sfmt); + + wait; + end process; + +end; diff --git a/testsuite/gna/issue2097/tb_fixed3.vhdl b/testsuite/gna/issue2097/tb_fixed3.vhdl new file mode 100644 index 000000000..839930710 --- /dev/null +++ b/testsuite/gna/issue2097/tb_fixed3.vhdl @@ -0,0 +1,43 @@ +library IEEE; +context IEEE.IEEE_std_context; + +library work; +use work.my_fixed_pkg.all; + +entity tb_fixed is +end; + +architecture arch of tb_fixed is + +begin + + process + constant ref : real := -9.96484375; + + subtype stype is sfixed(7 downto -8); + + -- Subtype not allowed as size_res argument of to_sfixed: + -- constant input : std_logic_vector (stype'length-1 downto 0) := to_slv(to_sfixed(ref, stype)); + -- Therefore, a variable needs to be created: + variable fmt : stype; + constant input : std_logic_vector (stype'length-1 downto 0) := to_slv(to_sfixed(ref, fmt)); + + variable sfmt : fmt'subtype; + + procedure report_sfixed(arg: sfixed) is begin report to_string(to_real(arg)); end procedure; + + begin + report_sfixed(stype(input)); + report_sfixed(stype(signed(input))); + + -- CRASH + report to_string(fmt'subtype); + + -- However, sfmt, which is declared using fmt'subtype, does work + sfmt := stype(input); + report_sfixed(sfmt); + + wait; + end process; + +end; diff --git a/testsuite/gna/issue2097/testsuite.sh b/testsuite/gna/issue2097/testsuite.sh new file mode 100755 index 000000000..922abea62 --- /dev/null +++ b/testsuite/gna/issue2097/testsuite.sh @@ -0,0 +1,18 @@ +#! /bin/sh + +. ../../testenv.sh + +export GHDL_STD_FLAGS=--std=08 +analyze my_fixed_pkg.vhdl + +analyze tb_fixed1.vhdl +elab_simulate tb_fixed1 + +analyze tb_fixed2.vhdl +elab_simulate tb_fixed2 + +analyze_failure tb_fixed3.vhdl + +clean + +echo "Test successful" diff --git a/testsuite/gna/issue2098/test.vhdl b/testsuite/gna/issue2098/test.vhdl new file mode 100644 index 000000000..b2dedd731 --- /dev/null +++ b/testsuite/gna/issue2098/test.vhdl @@ -0,0 +1,156 @@ +library std; + use std.textio.all; + +package log is + + type t_level is (TRACE, DEBUG, INFO, WARN, ERROR); + + type t_config is record + level : t_level; + show_level : boolean; + time_unit : time; + show_sim_time : boolean; + prefix : string(1 to 32); + separator : string(1 to 3); + end record; + + type t_logger is protected + procedure set_config(c : t_config); + + procedure trace(msg : string); + procedure debug(msg : string); + procedure info(msg : string); + procedure warn(msg : string); + procedure error(msg : string); + end protected; + + shared variable logger : t_logger; + + procedure set_config(cfg : t_config); + + procedure trace(msg : string); + procedure debug(msg : string); + procedure info(msg : string); + procedure warn(msg : string); + procedure error(msg : string); + + function config( + level : t_level := INFO; + time_unit : time := ns; + prefix : string(1 to 32) := (others => nul); + separator : string(1 to 3) := ": " & nul; + show_level : boolean := true; + show_sim_time : boolean := true + ) return t_config; + +end package; + +package body log is + + procedure trace(msg : string) is begin logger.trace(msg); end procedure; + procedure debug(msg : string) is begin logger.debug(msg); end procedure; + procedure info(msg : string) is begin logger.info(msg); end procedure; + procedure warn(msg : string) is begin logger.warn(msg); end procedure; + procedure error(msg : string) is begin logger.error(msg); end procedure; + + type t_logger is protected body + + variable cfg : t_config := config; + + procedure set_config(c : t_config) is begin cfg := c; end procedure; + + procedure log(lvl : t_level; msg : string) is + constant MAX_TIME_LEN : positive := 32; + variable time : string(1 to MAX_TIME_LEN); + variable time_line : line; + + procedure trim_time(t : inout string) is + begin + for i in t'reverse_range loop + if t(i) = ' ' then time(i) := nul; else return; end if; + end loop; + end procedure; + begin + if lvl < cfg.level then return; end if; + + if cfg.show_sim_time then + write(time_line, now, left, MAX_TIME_LEN, cfg.time_unit); + time := time_line.all; + trim_time(time); + end if; + + write(output, t_level'image(lvl) & cfg.separator & time & cfg.separator & msg & LF); + end procedure; + + + procedure trace(msg : string) is begin log(TRACE, msg); end procedure; + procedure debug(msg : string) is begin log(DEBUG, msg); end procedure; + procedure info(msg : string) is begin log(INFO, msg); end procedure; + procedure warn(msg : string) is begin log(WARN, msg); end procedure; + procedure error(msg : string) is begin log(ERROR, msg); end procedure; + + procedure set_level(l : t_level) is + begin + cfg.level := l; + end procedure; + + end protected body; + + procedure set_config(cfg : t_config) is begin logger.set_config(cfg); end procedure; + + function config( + level : t_level := INFO; + time_unit : time := ns; + prefix : string(1 to 32) := (others => nul); + separator : string(1 to 3) := ": " & nul; + show_level : boolean := true; + show_sim_time : boolean := true + ) return t_config is + variable cfg : t_config; + begin + cfg.level := level; + cfg.show_level := show_level; + cfg.time_unit := time_unit; + cfg.show_sim_time := show_sim_time; + cfg.prefix := prefix; + cfg.separator := separator; + return cfg; + end function; + +end package body; +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library work; + use work.log; + +entity test is +end entity; + +architecture tb of test is + +begin + main : process is + variable l : log.t_logger; + begin + wait for 7.5 ns; + + log.set_config(log.config(log.TRACE)); + + log.trace("TRACE"); + log.debug("DEBUG"); + log.info("INFO"); + log.warn("WARN"); + log.error("ERROR" & LF); + + l.set_config(log.config(log.TRACE)); + l.trace("TRACE"); + l.debug("DEBUG"); + l.info("INFO"); + l.warn("WARN"); + l.error("ERROR"); + + std.env.finish; + end process; +end architecture; diff --git a/testsuite/gna/issue2098/testsuite.sh b/testsuite/gna/issue2098/testsuite.sh new file mode 100755 index 000000000..1d84c0f57 --- /dev/null +++ b/testsuite/gna/issue2098/testsuite.sh @@ -0,0 +1,11 @@ +#! /bin/sh + +. ../../testenv.sh + +export GHDL_STD_FLAGS=--std=08 +analyze test.vhdl +elab_simulate test + +clean + +echo "Test successful" diff --git a/testsuite/gna/issue2100/ent.vhdl b/testsuite/gna/issue2100/ent.vhdl new file mode 100644 index 000000000..6b93d3014 --- /dev/null +++ b/testsuite/gna/issue2100/ent.vhdl @@ -0,0 +1,17 @@ +library ieee; +context ieee.ieee_std_context; + +entity ent is + port ( + din : in unsigned(15 downto 0); + dout : out unsigned(31 downto 0) + ); +end ent; + +architecture arch of ent is + +begin + + dout <= resize(din, dout'subtype); + +end architecture; diff --git a/testsuite/gna/issue2100/testsuite.sh b/testsuite/gna/issue2100/testsuite.sh new file mode 100755 index 000000000..f4ccfe70e --- /dev/null +++ b/testsuite/gna/issue2100/testsuite.sh @@ -0,0 +1,13 @@ +#! /bin/sh + +. ../../testenv.sh + +export GHDL_STD_FLAGS=--std=08 +analyze_failure ent.vhdl 2> log.err +if grep 'no overloaded function' log.err; then + exit 1 +fi + +clean + +echo "Test successful" diff --git a/testsuite/gna/issue2101/ent.vhdl b/testsuite/gna/issue2101/ent.vhdl new file mode 100644 index 000000000..54d0be346 --- /dev/null +++ b/testsuite/gna/issue2101/ent.vhdl @@ -0,0 +1,21 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity ent is + port ( + clk: in std_logic; + reset: in std_logic); +end entity; + +architecture a of ent is +begin + foo: process(clk, reset) + variable counter: integer range 0 to 15; + begin + if reset = '1' then + counter := counter'high; + elsif rising_edge(clk) then + counter := counter - 1; + end if; + end process; +end; diff --git a/testsuite/gna/issue2101/testsuite.sh b/testsuite/gna/issue2101/testsuite.sh new file mode 100755 index 000000000..9e7e2a886 --- /dev/null +++ b/testsuite/gna/issue2101/testsuite.sh @@ -0,0 +1,9 @@ +#! /bin/sh + +. ../../testenv.sh + +analyze_failure ent.vhdl + +clean + +echo "Test successful" diff --git a/testsuite/gna/issue2103/pkg_logic_misc.vhdl b/testsuite/gna/issue2103/pkg_logic_misc.vhdl new file mode 100644 index 000000000..8a8bdba00 --- /dev/null +++ b/testsuite/gna/issue2103/pkg_logic_misc.vhdl @@ -0,0 +1,155 @@ +
------------------------------------------------------------------------------
-- ____ _____________ __ --
-- / __ \/ ____/ ___/\ \/ / _ _ _ --
-- / / / / __/ \__ \ \ / / \ / \ / \ --
-- / /_/ / /___ ___/ / / / = ( M | S | K )= --
-- /_____/_____//____/ /_/ \_/ \_/ \_/ --
-- --
------------------------------------------------------------------------------
--! @copyright Copyright 2022 DESY
--! SPDX-License-Identifier: CERN-OHL-W-2.0
------------------------------------------------------------------------------
--! @date 2022-06-07
--! @author Andrea Bellandi
--! @email andrea.bellandi@desy.de
------------------------------------------------------------------------------
--! @brief
--! Miscellaneous logic utilities
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--!-------------------------------------------------------
--! Miscellaneous logic functions. All ported functions from
--! IEEE.std_logic_misc belongs here.
package logic_misc is
--!-------------------------------------------------------
--! f_to_std_logic:
--! Converts std_logic to boolean.
function f_to_std_logic (arg: boolean) return std_logic;
--!-------------------------------------------------------
--! f_to_boolean:
--! Converts std_logic to boolean
function f_to_boolean (arg: std_logic) return boolean;
--!-------------------------------------------------------
--! f_all_ones:
--! Checks whether all bits of **arg** are equal to '1'.
--! Equivalent to _and_reduce_.
function f_all_ones (arg: std_logic_vector) return std_logic;
--!-------------------------------------------------------
--! f_all_zeroes:
--! Checks wheter all bits of **arg** are equal to '0'.
--! Equivalent to _nor_reduce_.
function f_all_zeroes (arg: std_logic_vector) return std_logic;
--!-------------------------------------------------------
--! f_odd_ones:
--! Return '1' if an odd number of bits in **arg** are '1'.
--! Equivalent to _xor_reduce_.
function f_odd_ones (arg: std_logic_vector) return std_logic;
--!-------------------------------------------------------
--! f_even_ones:
--! Return '1' if an even number of bits in **arg** are '1'.
--! Return '1' if zero bits in **arg** are '1'.
--! Equivalent to _xnor_reduce_.
function f_even_ones (arg: std_logic_vector) return std_logic;
--!-------------------------------------------------------
--! f_odd_zeroes:
--! Return '1' if an odd number of bits in **arg** are '0'.
--! Equivalent to _xor_reduce_.
function f_odd_zeroes (arg: std_logic_vector) return std_logic;
--!-------------------------------------------------------
--! f_even_zeroes:
--! Return '1' if an even number of bits in **arg** are '0'.
--! Return '1' if zero bits in **arg** are '0'.
--! Equivalent to _xnor_reduce_.
function f_even_zeroes (arg: std_logic_vector) return std_logic;
-- vsg_off function_101
--!-------------------------------------------------------
--! or_reduce:
--! Reduction of bits in **arg** with the **or** logical operator.
--! Port of nonstandard _ieee.std_logic_misc.or_reduce_
function or_reduce (arg: std_logic_vector) return std_logic;
--!-------------------------------------------------------
--! and_reduce:
--! Reduction of bits in **arg** with the **and** logical operator.
--! Port of nonstandard _ieee.std_logic_misc.and_reduce_
function and_reduce (arg: std_logic_vector) return std_logic;
--!-------------------------------------------------------
--! xor_reduce:
--! Reduction of bits in **arg** with the **xor** logical operator.
--! Port of nonstandard _ieee.std_logic_misc.xor_reduce_
function xor_reduce (arg: std_logic_vector) return std_logic;
--!------------------------- + --! nor_reduce: + --! Negated reduction of bits in **arg** with the **or** logical operator. + --! Port of nonstandard _ieee.std_logic_misc.nor_reduce_ + + function nor_reduce (arg: std_logic_vector) return std_logic; + + --!------------------------------------------------------- + --! nand_reduce: + --! Negated reduction of bits in **arg** with the **and** logical operator. + --! Port of nonstandard _ieee.std_logic_misc.nand_reduce_ + + function nand_reduce (arg: std_logic_vector) return std_logic; + + --!------------------------------------------------------- + --! xnor_reduce: + --! Negated reduction of bits in **arg** with the **xor** logical operator. + --! Port of nonstandard _ieee.std_logic_misc.xnor_reduce_ + + function xnor_reduce (arg: std_logic_vector) return std_logic; + +-- vsg_on + +end package logic_misc; + +package body logic_misc is + + function f_to_std_logic (arg: boolean) return std_logic is + begin + + if (arg) then + return '1'; + else + return '0'; + end if; + + end function; + + function f_to_boolean (arg: std_logic) return boolean is + begin + + return arg = '1'; + + end function; + + function f_all_ones (arg: std_logic_vector) return std_logic is + + constant C_ONES : std_logic_vector(arg'length - 1 downto 0) := + ( + others => '1' + ); + + begin + + return f_to_std_logic(arg = C_ONES); + + end function; + + function f_all_zeroes (arg: std_logic_vector) return std_logic is + + constant C_ZEROES : std_logic_vector(arg'length - 1 downto 0) := + ( + others => '0' + ); + + begin + + return f_to_std_logic(arg = C_ZEROES); + + end function; + + function f_odd_ones (arg: std_logic_vector) return std_logic is + + variable var_result : std_logic := '0'; + + begin + + for i in arg'low to arg'high loop + + var_result := var_result xor arg(i); + + end loop; + + return var_result; + + end function; + + function f_even_ones (arg: std_logic_vector) return std_logic is + begin + + return not f_odd_ones(arg); + + end function; + + function f_odd_zeroes (arg: std_logic_vector) return std_logic is + begin + + return f_odd_ones(not arg); + + end function; + + function f_even_zeroes (arg: std_logic_vector) return std_logic is + begin + + return not f_odd_zeroes(arg); + + end function; + + -- vsg_off function_101 + + function or_reduce (arg: std_logic_vector) return std_logic is + begin + + return not f_all_zeroes(arg); + + end function; + + function and_reduce (arg: std_logic_vector) return std_logic is + begin + + return f_all_ones(arg); + + end function; + + function xor_reduce (arg: std_logic_vector) return std_logic is + begin + + return f_odd_ones(arg); + + end function; + + function nor_reduce (arg: std_logic_vector) return std_logic is + begin + + return f_all_zeroes(arg); + + end function; + + function nand_reduce (arg: std_logic_vector) return std_logic is + begin + + return not f_all_ones(arg); + + end function; + + function xnor_reduce (arg: std_logic_vector) return std_logic is + begin + + return f_even_ones(arg); + + end function; + +-- vsg_on + +end package body logic_misc; diff --git a/testsuite/gna/issue2103/pkg_math_signed.vhdl b/testsuite/gna/issue2103/pkg_math_signed.vhdl new file mode 100644 index 000000000..8dedeb43c --- /dev/null +++ b/testsuite/gna/issue2103/pkg_math_signed.vhdl @@ -0,0 +1,110 @@ + +------------------------------------------------------------------------------ +-- ____ _____________ __ -- +-- / __ \/ ____/ ___/\ \/ / _ _ _ -- +-- / / / / __/ \__ \ \ / / \ / \ / \ -- +-- / /_/ / /___ ___/ / / / = ( M | S | K )= -- +-- /_____/_____//____/ /_/ \_/ \_/ \_/ -- +-- -- +------------------------------------------------------------------------------ +--! @copyright Copyright 2020-2022 DESY +--! SPDX-License-Identifier: CERN-OHL-W-2.0 +------------------------------------------------------------------------------ +--! @date 2020-10-02/2022-04-01 +--! @author Lukasz Butkowski <lukasz.butkowski@desy.de> +--! @author Michael Buechler <michael.buechler@desy.de> +------------------------------------------------------------------------------ +--! @brief +--! Provides math function/procedures with signed signals +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.math_utils.all; +use work.logic_misc.all; + +package math_signed is + + --! Saturate *arg* to the maximum or minimum representable value depending on + --! sat + function f_saturate (arg : signed; sat : t_saturation) return signed; + + --! Resize with saturation protection + function f_resize_sat (arg : signed; length : positive) return signed; + + --! Resize with saturation protection and saturation flag + --! Like the <<f_resize_sat>> function but also sets an overflow bit. + --! To be able to combine this with another preceding operation like shift_right + --! in a process, the argument 'arg' must be a variable instead of a signal. + procedure prd_resize_sat ( + signal arg : in signed; + constant length : in positive; + signal result : out signed; + signal sat : out t_saturation + ); + +end package math_signed; + +--****************************************************************************** + +package body math_signed is + + function f_saturate (arg : signed; sat : t_saturation) return signed is + begin + + if (sat = ST_SAT_OVERFLOWN) then + return f_max_val_of(arg); + elsif (sat = ST_SAT_UNDERFLOWN) then + return f_min_val_of(arg); + else + return arg; + end if; + + end function f_saturate; + + function f_resize_sat (arg : signed; length : natural) return signed is + + variable var_result : signed(length - 1 downto 0); + + begin + + prd_resize_sat(arg => arg, length => length, result => var_result); + return var_result; + + end function; + + procedure prd_resize_sat ( + signal arg : in signed; + constant length : in positive; + signal result : out signed; + signal sat : out t_saturation + ) is + + variable var_sat : t_saturation; + + begin + + if (length >= arg'length) then + var_sat := ST_SAT_OK; + else + -- check overflow saturation + if (arg(arg'high) = '0' and + f_all_zeroes(arg(arg'high-1 downto length - 1)) = '0') then + var_sat := ST_SAT_OVERFLOWN; + -- check underflow saturation + elsif (arg(arg'high) = '1' and + f_all_ones(arg(arg'high-1 downto length - 1)) = '0') then + var_sat := ST_SAT_UNDERFLOWN; + else + var_sat := ST_SAT_OK; + end if; + result <= f_saturate(resize(arg, length), var_sat); + sat <= var_sat; + end if; + + end procedure prd_resize_sat; + +end package body math_signed; diff --git a/testsuite/gna/issue2103/pkg_math_utils.vhdl b/testsuite/gna/issue2103/pkg_math_utils.vhdl new file mode 100644 index 000000000..4d3804082 --- /dev/null +++ b/testsuite/gna/issue2103/pkg_math_utils.vhdl @@ -0,0 +1,250 @@ +------------------------------------------------------------------------------ +-- ____ _____________ __ -- +-- / __ \/ ____/ ___/\ \/ / _ _ _ -- +-- / / / / __/ \__ \ \ / / \ / \ / \ -- +-- / /_/ / /___ ___/ / / / = ( M | S | K )= -- +-- /_____/_____//____/ /_/ \_/ \_/ \_/ -- +-- -- +------------------------------------------------------------------------------ +--! @copyright Copyright 2022 DESY +--! SPDX-License-Identifier: CERN-OHL-W-2.0 +------------------------------------------------------------------------------ +--! @date 2022-04-01 +--! @author Michael Buechler <michael.buechler@desy.de> +--! @author Lukasz Butkowski <lukasz.butkowski@desy.de> +------------------------------------------------------------------------------ +--! @brief +--! Math utilities +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; + +--! Package of mathematical utilities and support functions +package math_utils is + + --! Saturation status after an operation. + type t_saturation is (ST_SAT_OK, ST_SAT_OVERFLOWN, ST_SAT_UNDERFLOWN); + + --! The encoding for _t_staturation_ is + --! + --! * ST_SAT_OK = "00" (No saturation) + --! * ST_SAT_OVERFLOWN = "10" (Operation has overflown) + --! * ST_SAT_UNDERFLOWN = "01" (Operation has underflown) + attribute enum_encoding : string; + attribute enum_encoding of t_saturation : type is "00 10 01"; + + --! f_bit_length: + --! Comparable to Python's int.bit_length(), + --! but when arg is negative, calculate for two's complement. + --! Attention: returns 1 for argument -1. + --! When arg is zero, return 0. + function f_bit_length (arg: integer) return integer; + + --! f_unsigned_length: + --! Calculates the minimum unsigned signal length to store **arg**, + --! When arg is zero, return 0. + function f_unsigned_length (arg: natural) return natural; + + --! Calculates the minimum signed signal length to store *arg*, + --! When arg is zero, return 0. + function f_signed_length (arg: integer) return integer; + + --! f_maximum: + --! Porting of 'maximum' from VHDL 08' not present in the + --! 93' standard. + function f_maximum (a, b: integer) return integer; + + --! f_minimum: + --! Porting of 'minimum' from VHDL 08' not present in the + --! 93' standard + function f_minimum (a, b: integer) return integer; + + --! f_max_val_for_length: + --! Returns the maximum value representable by a numeric type of length + --! _length_ and sign _sign_. + function f_max_val_for_length (length: natural; sign : boolean) return integer; + + function f_max_val_of (arg: unsigned) return unsigned; + + --! f_max_val_of: + --! Returns the maximum value representable by a numeric type. + --! Signed and unsigned version. + function f_max_val_of (arg: signed) return signed; + + --! f_max_val_for_length: + --! Returns the maximum value representable by a numeric type of length + --! _length_ and sign _sign_. + function f_min_val_for_length (length: natural; sign : boolean) return integer; + + function f_min_val_of (arg: unsigned) return unsigned; + + --! f_min_val_of: + --! Returns the minimum value representable by a numeric type. + --! Signed and unsigned version. + function f_min_val_of (arg: signed) return signed; + + function f_is_max (arg: unsigned) return boolean; + + --! f_is_max: + --! Checks whether a signal is at its maximum value. + --! Signed and unsigned version. + function f_is_max (arg: signed) return boolean; + + function f_is_min (arg: unsigned) return boolean; + + --! f_is_min: + --! Checks whether a signal is at its minimum value. + --! Signed and unsigned version. + function f_is_min (arg: signed) return boolean; + +end package math_utils; + +--****************************************************************************** + +--****************************************************************************** + +package body math_utils is + + function f_bit_length (arg: integer) return integer is + begin + + if (arg = 0) then + return 0; + elsif (arg > 0) then + return integer(ceil(log2(real(arg + 1)))); + else + return integer(ceil(log2(-real(arg)))) + 1; + end if; + + end function; + + function f_unsigned_length (arg: natural) return natural is + begin + + return natural(f_bit_length(integer(arg))); + + end function; + + function f_signed_length (arg: integer) return integer is + begin + + if (arg >= 0) then + return f_bit_length(arg) + 1; + else + return f_bit_length(arg); + end if; + + end function; + + function f_maximum (a, b: integer) return integer is + begin + + if (a > b) then + return a; + else + return b; + end if; + + end function; + + function f_minimum (a, b: integer) return integer is + begin + + if (a < b) then + return a; + else + return b; + end if; + + end function; + + function f_max_val_for_length (length: natural; sign : boolean) return integer is + + constant C_SMAX : integer := (2 ** (length - 1)) - 1; + constant C_UMAX : integer := (2 ** length) - 1; + + begin + + if (sign) then + return C_SMAX; + else + return C_UMAX; + end if; + + end function; + + function f_max_val_of (arg: unsigned) return unsigned is + begin + + return to_unsigned(f_max_val_for_length(arg'length, false), arg'length); + + end function; + + function f_max_val_of (arg: signed) return signed is + begin + + return to_signed(f_max_val_for_length(arg'length, true), arg'length); + + end function; + + function f_min_val_for_length (length: natural; sign : boolean) return integer is + + constant C_SMIN : integer := - (2 ** (length - 1)); + constant C_UMIN : integer := 0; + + begin + + if (sign) then + return C_SMIN; + else + return C_UMIN; + end if; + + end function; + + function f_min_val_of (arg: unsigned) return unsigned is + begin + + return to_unsigned(f_min_val_for_length(arg'length, false), arg'length); + + end function; + + function f_min_val_of (arg: signed) return signed is + begin + + return to_signed(f_min_val_for_length(arg'length, true), arg'length); + + end function; + + function f_is_max (arg: unsigned) return boolean is + begin + + return arg = f_max_val_of(arg); + + end; + + function f_is_max (arg: signed) return boolean is + begin + + return arg = f_max_val_of(arg); + + end; + + function f_is_min (arg: unsigned) return boolean is + begin + + return arg = f_min_val_of(arg); + + end; + + function f_is_min (arg: signed) return boolean is + begin + + return arg = f_min_val_of(arg); + + end; + +end package body math_utils; diff --git a/testsuite/gna/issue2103/repro.vhdl b/testsuite/gna/issue2103/repro.vhdl new file mode 100644 index 000000000..0393ad2c5 --- /dev/null +++ b/testsuite/gna/issue2103/repro.vhdl @@ -0,0 +1,10 @@ +package repro is + function f (arg : bit; length : natural) return bit; +end repro; + +package body repro is + function f (arg : bit; length : positive) return bit is + begin + return arg; + end; +end repro; diff --git a/testsuite/gna/issue2103/repro2.vhdl b/testsuite/gna/issue2103/repro2.vhdl new file mode 100644 index 000000000..7bbeefe10 --- /dev/null +++ b/testsuite/gna/issue2103/repro2.vhdl @@ -0,0 +1,10 @@ +package repro2 is + function f (arg : bit; length : string) return bit; +end repro2; + +package body repro2 is + function f (arg : bit; length : bit_vector) return bit is + begin + return arg; + end; +end repro2; diff --git a/testsuite/gna/issue2103/repro3.vhdl b/testsuite/gna/issue2103/repro3.vhdl new file mode 100644 index 000000000..9150c27eb --- /dev/null +++ b/testsuite/gna/issue2103/repro3.vhdl @@ -0,0 +1,13 @@ +package repro3 is + constant a1 : natural := 1; + constant a2 : natural := 1; + + function f (arg : bit; length : string (1 to a1)) return bit; +end; + +package body repro3 is + function f (arg : bit; length : string (1 to a2)) return bit is + begin + return arg; + end; +end; diff --git a/testsuite/gna/issue2103/repro4.vhdl b/testsuite/gna/issue2103/repro4.vhdl new file mode 100644 index 000000000..bc5c6048d --- /dev/null +++ b/testsuite/gna/issue2103/repro4.vhdl @@ -0,0 +1,16 @@ +package repro4 is + constant a1 : natural := 1; + constant a2 : natural := 1; + + alias b1 : natural is a1; + alias b2 : natural is a2; + + function f (arg : bit; length : string (1 to b1)) return bit; +end; + +package body repro4 is + function f (arg : bit; length : string (1 to b2)) return bit is + begin + return arg; + end; +end; diff --git a/testsuite/gna/issue2103/repro5.vhdl b/testsuite/gna/issue2103/repro5.vhdl new file mode 100644 index 000000000..9eca4a391 --- /dev/null +++ b/testsuite/gna/issue2103/repro5.vhdl @@ -0,0 +1,13 @@ +package repro4 is + alias n1 is natural; + alias n2 is natural; + + function f (arg : bit; length : n1) return bit; +end; + +package body repro4 is + function f (arg : bit; length : n2) return bit is + begin + return arg; + end; +end; diff --git a/testsuite/gna/issue2103/testsuite.sh b/testsuite/gna/issue2103/testsuite.sh new file mode 100755 index 000000000..7bc24fd37 --- /dev/null +++ b/testsuite/gna/issue2103/testsuite.sh @@ -0,0 +1,17 @@ +#! /bin/sh + +. ../../testenv.sh + +analyze_failure repro.vhdl +analyze_failure repro2.vhdl +analyze_failure repro3.vhdl +analyze_failure repro4.vhdl +analyze_failure repro5.vhdl + +analyze pkg_logic_misc.vhdl +analyze pkg_math_utils.vhdl +analyze_failure pkg_math_signed.vhdl + +clean + +echo "Test successful" diff --git a/testsuite/gna/issue2104/e.vhdl b/testsuite/gna/issue2104/e.vhdl new file mode 100644 index 000000000..4c83a0824 --- /dev/null +++ b/testsuite/gna/issue2104/e.vhdl @@ -0,0 +1,14 @@ +entity e is +end; + +architecture a of e is + function outer(arg : integer) return integer is + function inner(arg : integer) return integer is + begin + return outer(0); + end; + begin + return inner(0); + end; +begin +end; diff --git a/testsuite/gna/issue2104/e2.vhdl b/testsuite/gna/issue2104/e2.vhdl new file mode 100644 index 000000000..e4690f2b7 --- /dev/null +++ b/testsuite/gna/issue2104/e2.vhdl @@ -0,0 +1,18 @@ +entity e2 is +end; + +architecture a of e2 is + function outer(arg : integer) return integer is + function inner1(arg : integer) return integer is + begin + return arg + 1; + end; + function inner2(arg : integer) return integer is + begin + return inner1(arg + 2); + end; + begin + return inner2(arg + 3); + end; +begin +end; diff --git a/testsuite/gna/issue2104/e2b.vhdl b/testsuite/gna/issue2104/e2b.vhdl new file mode 100644 index 000000000..de1422675 --- /dev/null +++ b/testsuite/gna/issue2104/e2b.vhdl @@ -0,0 +1,19 @@ +entity e2b is + generic (gen1 : natural := 5); +end; + +architecture a of e2b is + function outer(arg : integer) return integer is + function inner1(arg : integer) return integer is + begin + return arg + gen1; + end; + function inner2(arg : integer) return integer is + begin + return inner1(arg + 2); + end; + begin + return inner2(arg + 3); + end; +begin +end; diff --git a/testsuite/gna/issue2104/e2c.vhdl b/testsuite/gna/issue2104/e2c.vhdl new file mode 100644 index 000000000..e3ecae001 --- /dev/null +++ b/testsuite/gna/issue2104/e2c.vhdl @@ -0,0 +1,15 @@ +entity e2c is + generic (gen1 : natural := 5); +end; + +architecture a of e2c is + function outer(arg : integer) return integer is + function inner1(arg : integer) return integer is + begin + return arg + gen1; + end; + begin + return inner1(arg + 3); + end; +begin +end; diff --git a/testsuite/gna/issue2104/e2d.vhdl b/testsuite/gna/issue2104/e2d.vhdl new file mode 100644 index 000000000..0b541fc47 --- /dev/null +++ b/testsuite/gna/issue2104/e2d.vhdl @@ -0,0 +1,19 @@ +entity e2d is + generic (gen1 : natural := 5); +end; + +architecture a of e2d is + function outer(arg : integer) return integer is + function inner1(arg : integer) return integer is + begin + return arg + 1; + end; + function inner2(arg : integer) return integer is + begin + return inner1(arg + 2); + end; + begin + return gen1 + inner2(arg + 3); + end; +begin +end; diff --git a/testsuite/gna/issue2104/e3.vhdl b/testsuite/gna/issue2104/e3.vhdl new file mode 100644 index 000000000..f3641b52e --- /dev/null +++ b/testsuite/gna/issue2104/e3.vhdl @@ -0,0 +1,18 @@ +entity e3 is +end; + +architecture a of e3 is + function outer(arg : integer) return integer is + function inner1(arg : integer) return integer is + function inner2(arg : integer) return integer is + begin + return arg + 1; + end; + begin + return inner2(0); + end; + begin + return inner1(0); + end; +begin +end; diff --git a/testsuite/gna/issue2104/testsuite.sh b/testsuite/gna/issue2104/testsuite.sh new file mode 100755 index 000000000..02342e717 --- /dev/null +++ b/testsuite/gna/issue2104/testsuite.sh @@ -0,0 +1,12 @@ +#! /bin/sh + +. ../../testenv.sh + +for f in e e2 e2b e2c e2d e3; do + analyze $f.vhdl + elab_simulate $f +done + +clean + +echo "Test successful" diff --git a/testsuite/gna/issue2110/conf1.vhdl b/testsuite/gna/issue2110/conf1.vhdl new file mode 100644 index 000000000..f3c37ca97 --- /dev/null +++ b/testsuite/gna/issue2110/conf1.vhdl @@ -0,0 +1,3 @@ +configuration" +" +for
\ No newline at end of file diff --git a/testsuite/gna/issue2110/psl1.vhdl b/testsuite/gna/issue2110/psl1.vhdl new file mode 100644 index 000000000..69d0df631 --- /dev/null +++ b/testsuite/gna/issue2110/psl1.vhdl @@ -0,0 +1 @@ +entity begin restrict[*to 0
\ No newline at end of file diff --git a/testsuite/gna/issue2110/psl2.vhdl b/testsuite/gna/issue2110/psl2.vhdl new file mode 100644 index 000000000..01fbea406 --- /dev/null +++ b/testsuite/gna/issue2110/psl2.vhdl @@ -0,0 +1 @@ +architecturerestrict[=to 0
\ No newline at end of file diff --git a/testsuite/gna/issue2110/retid.vhdl b/testsuite/gna/issue2110/retid.vhdl new file mode 100644 index 000000000..1b5482847 --- /dev/null +++ b/testsuite/gna/issue2110/retid.vhdl @@ -0,0 +1 @@ +package function return g.b of
\ No newline at end of file diff --git a/testsuite/gna/issue2110/testsuite.sh b/testsuite/gna/issue2110/testsuite.sh new file mode 100755 index 000000000..0524390f9 --- /dev/null +++ b/testsuite/gna/issue2110/testsuite.sh @@ -0,0 +1,13 @@ +#! /bin/sh + +. ../../testenv.sh + +export GHDL_STD_FLAGS=--std=08 +for f in conf1.vhdl psl1.vhdl psl2.vhdl retid.vhdl; do + analyze_failure $f +done + +clean + +echo "Test successful" + diff --git a/testsuite/gna/issue2115/ent.vhdl b/testsuite/gna/issue2115/ent.vhdl new file mode 100644 index 000000000..23407ccf5 --- /dev/null +++ b/testsuite/gna/issue2115/ent.vhdl @@ -0,0 +1,19 @@ +entity ent is +end entity; + +architecture a of ent is +begin + process + variable b : boolean; + variable l : std.textio.line; + begin + b := false; + std.textio.write(l, b); + report l.all & " should be false"; + l := null; + b := true; + std.textio.write(l, b); + report l.all & " should be true"; + wait; + end process; +end; diff --git a/testsuite/gna/issue2115/testsuite.sh b/testsuite/gna/issue2115/testsuite.sh new file mode 100755 index 000000000..9fbe06a6c --- /dev/null +++ b/testsuite/gna/issue2115/testsuite.sh @@ -0,0 +1,20 @@ +#! /bin/sh + +. ../../testenv.sh + +export GHDL_STD_FLAGS=--std=08 +analyze ent.vhdl +elab_simulate ent + +analyze tst08.vhdl +elab_simulate tst08 + +clean + +export GHDL_STD_FLAGS=--std=93 +analyze tst93.vhdl +elab_simulate tst93 + +clean + +echo "Test successful" diff --git a/testsuite/gna/issue2115/tst08.vhdl b/testsuite/gna/issue2115/tst08.vhdl new file mode 100644 index 000000000..57ccfda2a --- /dev/null +++ b/testsuite/gna/issue2115/tst08.vhdl @@ -0,0 +1,24 @@ +entity tst08 is +end entity; + +use std.textio.all; + +architecture a of tst08 is +begin + process + variable l : line; + begin + write(l, false); + assert l.all = "false" severity failure; + deallocate (l); + write(l, true); + assert l.all = "true" severity failure; + + assert boolean'image(true) = "true" severity failure; + assert boolean'image(false) = "false" severity failure; + + assert to_string(true) = "true" severity failure; + assert to_string(false) = "false" severity failure; + wait; + end process; +end; diff --git a/testsuite/gna/issue2115/tst93.vhdl b/testsuite/gna/issue2115/tst93.vhdl new file mode 100644 index 000000000..5fb36fbb8 --- /dev/null +++ b/testsuite/gna/issue2115/tst93.vhdl @@ -0,0 +1,21 @@ +entity tst93 is +end entity; + +use std.textio.all; + +architecture a of tst93 is +begin + process + variable l : line; + begin + write(l, false); + assert l.all = "FALSE" severity failure; + deallocate (l); + write(l, true); + assert l.all = "TRUE" severity failure; + + assert boolean'image(true) = "true" severity failure; + assert boolean'image(false) = "false" severity failure; + wait; + end process; +end; diff --git a/testsuite/gna/issue2116/aspect01.vhdl b/testsuite/gna/issue2116/aspect01.vhdl new file mode 100644 index 000000000..a2005b2e3 --- /dev/null +++ b/testsuite/gna/issue2116/aspect01.vhdl @@ -0,0 +1,6 @@ +library ieee;use ieee.std_logic_1164.all;entity dut is +port(sig_i:std_logic_vector;sig_o:out std_logic_vector);end entity;architecture a of dut is +begin sig_o<=sig_i;end architecture;library ieee;use ieee.std_logic_1164.all;entity tb is +end entity;architecture h of tb is +signal s:std_logic_vector(0 to 0);signal s0:std_logic_vector(0 downto 0);begin process begin +wait for ns;report to_string(0);report to_string(0);end process;t:entity k't port map(0);end architecture; diff --git a/testsuite/gna/issue2116/aspect02.vhdl b/testsuite/gna/issue2116/aspect02.vhdl new file mode 100644 index 000000000..22830d6ba --- /dev/null +++ b/testsuite/gna/issue2116/aspect02.vhdl @@ -0,0 +1,7 @@ +entity tb is +end entity; + +architecture h of tb is +begin + t:entity k't port map(0); +end architecture; diff --git a/testsuite/gna/issue2116/aspect03.vhdl b/testsuite/gna/issue2116/aspect03.vhdl new file mode 100644 index 000000000..4d0875615 --- /dev/null +++ b/testsuite/gna/issue2116/aspect03.vhdl @@ -0,0 +1,6 @@ +library ieee;use ieee.std_logic_1164.all;entity dut is +port(sig_i:std_logic_vector;sig_o:out std_logic_vector);end entity;architecture a of dut is +begin sig_o<=sig_i;end architecture;library ieee;use ieee.std_logic_1164.all;entity tb is +end entity;architecture h of tb is +signal s:std_logic_vector(0 to 0);signal s0:std_logic_vector(0 downto 0);begin process begin +wait for ns;report to_string(0);report to_string(0);end process;t:entity k't port map(0);end architecture;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr1.vhdl b/testsuite/gna/issue2116/attr1.vhdl new file mode 100644 index 000000000..b1b1082dd --- /dev/null +++ b/testsuite/gna/issue2116/attr1.vhdl @@ -0,0 +1,6 @@ +library ieee;use ieee.std_logic_1164;entity ghdlcrash is +port(a:std'u);end ghdlcrash;architecture h of g is-- +function m(a:n)return l is +variable m:u;begin-- +end function;begin +end architecture;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr10.vhdl b/testsuite/gna/issue2116/attr10.vhdl new file mode 100644 index 000000000..617b90690 --- /dev/null +++ b/testsuite/gna/issue2116/attr10.vhdl @@ -0,0 +1,4 @@ +library ieee;use ieee.std_logic_1164;use ieee.numeric_bit_unsigned.all;entity le0el0 is generic(G:integer;G0:integer);port(c:std'l;s:c;-- +w:i);end entity le0el0;architecture synthesis of l is +begin +end architecture synthesis;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr11.vhdl b/testsuite/gna/issue2116/attr11.vhdl new file mode 100644 index 000000000..3e362b268 --- /dev/null +++ b/testsuite/gna/issue2116/attr11.vhdl @@ -0,0 +1,4 @@ +library ieee;use ieee.std_logic_1164.all;entity if01 is port(a:std_logic;b:std_logic;n:std_logic;l:std_logic;cl0:std_logic;s:std_logic;s0:std_logic);end;architecture behav of if01 is +begin process(cl0)is +variable t:std'l;begin +if(0)then if'0'then end if;end if;end process;end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr12.vhdl b/testsuite/gna/issue2116/attr12.vhdl new file mode 100644 index 000000000..f04d4730c --- /dev/null +++ b/testsuite/gna/issue2116/attr12.vhdl @@ -0,0 +1,5 @@ +package gen0 is +generic(v:natural:=0);function get return natural;end gen0;package body gen0 is +function get return natural is begin return 0;end get;end;package gen2 is generic(package pkg is new work.gen0 generic map(<>));function get2 return natural;end gen2;package body gen2 is use pkg.all;function get2 return natural is begin return get;end;end;package pkg0 is new work.gen0;package p is new work.gen2 generic map(work.pkg0);entity tb is +end;architecture behav of tb is +begin assert work'p;end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr13.vhdl b/testsuite/gna/issue2116/attr13.vhdl new file mode 100644 index 000000000..c193ee17f --- /dev/null +++ b/testsuite/gna/issue2116/attr13.vhdl @@ -0,0 +1,4 @@ +library ieee;use ieee.numeric_std.all;use ieee.std_logic_1164.all;entity t is generic(e:boolean:=false);port(k:std'i);end;architecture a of g is type e is array(0)of m;signal w:r range 0 to 0;signal r:t;signal i:n;begin m<='0'when(0);process(a)begin if(0)then +if 0 then(0)<=0;end if;if 0 then if 0 then end if;end if;end if;if 0 then +if 0 then +end if;end if;end process;end;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr14.vhdl b/testsuite/gna/issue2116/attr14.vhdl new file mode 100644 index 000000000..a5893144a --- /dev/null +++ b/testsuite/gna/issue2116/attr14.vhdl @@ -0,0 +1,6 @@ +library ieee;use ieee.std_logic_1164;use ieee.numeric_bit.all;entity hello is +port(t:std'c;t:i(0));end hello;architecture behav of h is +signal v:d(0);begin +process(c)begin +if(0)then +if'0'then(0)<=0;end if;end if;end process;end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr15.vhdl b/testsuite/gna/issue2116/attr15.vhdl new file mode 100644 index 000000000..cc629345d --- /dev/null +++ b/testsuite/gna/issue2116/attr15.vhdl @@ -0,0 +1,6 @@ +library ieee;use ieee.std_logic_1164;entity t is +port(s:std'l);end entity;architecture a of t is +begin i;end architecture;library i;entity b is +end entity;architecture h of b is +signal n:r(0);signal s:s(0);begin process begin +end process;t(0);end architecture;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr16.vhdl b/testsuite/gna/issue2116/attr16.vhdl new file mode 100644 index 000000000..8a0242083 --- /dev/null +++ b/testsuite/gna/issue2116/attr16.vhdl @@ -0,0 +1,3 @@ +library ieee;use ieee.numeric_std.all;use ieee.std_logic_1164.all;entity t is generic(e:boolean:=false);port(l:std'c);end;architecture a of g is type y is array(0)of t;signal m:n;begin +y<='0'when(0)else'0'when(0)and(0);process(l)begin +if(0)then if 0 then(0)<=0;end if;if 0 then if 0 then end if;end if;end if;end process;end;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr17.vhdl b/testsuite/gna/issue2116/attr17.vhdl new file mode 100644 index 000000000..e17097790 --- /dev/null +++ b/testsuite/gna/issue2116/attr17.vhdl @@ -0,0 +1,6 @@ +library ieee;use ieee.std_logic_1164;use ieee.numeric_std.all;entity hello is +port(c:std'l;t:d(0));end hello;architecture behav of h is +signal v:d(0);begin +process(l)begin +if(0)then if'0'then +v<=0;end if;end if;end process;end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr18.vhdl b/testsuite/gna/issue2116/attr18.vhdl new file mode 100644 index 000000000..0866535cb --- /dev/null +++ b/testsuite/gna/issue2116/attr18.vhdl @@ -0,0 +1,7 @@ +library ieee;use ieee.std_logic_1164;use ieee.numeric_std.all;entity hello is +port(c:std'l;t:d(0));end hello;architecture behav of h is +signal v:d(0);begin +process(c)begin +if(0)then +if 0='0'then +s;end if;end if;end process;end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr19.vhdl b/testsuite/gna/issue2116/attr19.vhdl new file mode 100644 index 000000000..989d27a7b --- /dev/null +++ b/testsuite/gna/issue2116/attr19.vhdl @@ -0,0 +1,6 @@ +library ieee;use ieee.std_logic_1164;entity ghdlcrash is +port(a:std'u);end ghdlcrash;architecture o of g is-- +function m(a:n)return l is +variable m:u;begin-- +end function;begin +end architecture;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr2.vhdl b/testsuite/gna/issue2116/attr2.vhdl new file mode 100644 index 000000000..319dda8af --- /dev/null +++ b/testsuite/gna/issue2116/attr2.vhdl @@ -0,0 +1,3 @@ +entity a is + constant c : natural := std'u; +end; diff --git a/testsuite/gna/issue2116/attr20.vhdl b/testsuite/gna/issue2116/attr20.vhdl new file mode 100644 index 000000000..6f7fc3d59 --- /dev/null +++ b/testsuite/gna/issue2116/attr20.vhdl @@ -0,0 +1,6 @@ +library ieee;use ieee.std_logic_1164;library ieee;use ieee.std_logic_1164.all;entity ghdlcrash is +port(i:std'l);end ghdlcrash;architecture s of h is +function m(a:l)return n is +variable m:t;begin +end function;begin +end architecture;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr21.vhdl b/testsuite/gna/issue2116/attr21.vhdl new file mode 100644 index 000000000..146a86be8 --- /dev/null +++ b/testsuite/gna/issue2116/attr21.vhdl @@ -0,0 +1,5 @@ +library ieee;use ieee.std_logic_1164.all;entity dut is +port(sig_i:std_logic_vector;sig_o:out std_logic_vector);end entity;architecture a of dut is +begin sig_o<=sig_i;end architecture;library ieee;use ieee.std_logic_1164.all;entity tb is +end entity;architecture h of tb is +signal n:std_logic_vector(0 to 0);signal s:std'u(0);begin t port map(0);end architecture;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr22.vhdl b/testsuite/gna/issue2116/attr22.vhdl new file mode 100644 index 000000000..dca2466b2 --- /dev/null +++ b/testsuite/gna/issue2116/attr22.vhdl @@ -0,0 +1,6 @@ +library ieee;use ieee.std_logic_1164.all;entity dut is +port(sig_i:std_logic_vector;sig_o:out std_logic_vector);end entity;architecture a of dut is +begin sig_o<=sig_i;end architecture;library ieee;use ieee.std_logic_1164.all;entity tb is +end entity;architecture h of tb is +signal s0:std_logic_vector(0 downto 0);signal s:std_logic_vector(0 to 0);begin process begin +wait for ns;report to_string(0)+std'n;end process;end architecture;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr23.vhdl b/testsuite/gna/issue2116/attr23.vhdl new file mode 100644 index 000000000..53462d099 --- /dev/null +++ b/testsuite/gna/issue2116/attr23.vhdl @@ -0,0 +1,6 @@ +library ieee;use ieee.std_logic_1164;use ieee.numeric_std.all;entity hello is +port(c:std'l;t:d(0));end hello;architecture behav of h is +signal v:d(0);begin +process(c)begin +if(0)then +if'0'then('0')<=0;end if;end if;end process;end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr24.vhdl b/testsuite/gna/issue2116/attr24.vhdl new file mode 100644 index 000000000..bbd2787c5 --- /dev/null +++ b/testsuite/gna/issue2116/attr24.vhdl @@ -0,0 +1,3 @@ +library ieee;use ieee.numeric_std.all;use ieee.std_logic_1164.all;entity t is generic(type s;z:boolean:=false);port(l:std'l);end;architecture a of t is type t is array(0)of t;signal r:r range 0 to 0;signal d:r range 0 to 0;signal d:n;begin y<='0'when(0)and 0 else'0';m(0);process(l)begin +if(0)then if 0 then w<=0;end if;if 0 then +r<=0;end if;end if;end process;end;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr25.vhdl b/testsuite/gna/issue2116/attr25.vhdl new file mode 100644 index 000000000..a4b4aae96 --- /dev/null +++ b/testsuite/gna/issue2116/attr25.vhdl @@ -0,0 +1,6 @@ +package gen0 is +generic(v:natural:=0);function get return natural;end;package body gen0 is +function get return natural is +begin return 0;end;end;package gen2 is generic(package pkg is new work.gen0 generic map(<>));function get2 return natural;end;package body gen2 is use pkg.all;function get2 return natural is begin return get;end get2;end;package pkg0 is new work.gen0;package p is new work.gen2 generic map(work.pkg0);entity tb is +end;architecture behav of tb is +begin assert work'p;end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr26.vhdl b/testsuite/gna/issue2116/attr26.vhdl new file mode 100644 index 000000000..78ecc7092 --- /dev/null +++ b/testsuite/gna/issue2116/attr26.vhdl @@ -0,0 +1,3 @@ +library ieee;use ieee.numeric_std.all;use ieee.std_logic_1164.all;entity g is generic(type m;e:integer:=0;e0:boolean:=false);port(l:std'c);end;architecture a of g is type e;signal r:r range 0 to 0;signal r:r range 0 to 0;signal m:e;signal d:n;begin d(0);process(a)begin +if(0)then if 0 then m<=0;end if;if 0 then +elsif 0 then if 0 then r;end if;end if;end if;end process;end;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr3.vhdl b/testsuite/gna/issue2116/attr3.vhdl new file mode 100644 index 000000000..2dc324279 --- /dev/null +++ b/testsuite/gna/issue2116/attr3.vhdl @@ -0,0 +1,6 @@ +library ieee;use ieee.std_logic_1164.all;entity dut is +port(sig_i:std_logic_vector;sig_o:out std_logic_vector);end entity;architecture a of dut is +begin sig_o<=sig_i;end architecture;library ieee;use ieee.std_logic_1164;entity tb is +end entity;architecture h of tb is +signal n:std'r(0);signal s:s(0);begin process begin +end process;t(0);end architecture;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr4.vhdl b/testsuite/gna/issue2116/attr4.vhdl new file mode 100644 index 000000000..4993b0feb --- /dev/null +++ b/testsuite/gna/issue2116/attr4.vhdl @@ -0,0 +1,4 @@ +library ieee;use ieee.std_logic_1164;entity d is +port(s:std'r);end entity;architecture c of t is +begin +t;end architecture;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr5.vhdl b/testsuite/gna/issue2116/attr5.vhdl new file mode 100644 index 000000000..63a448073 --- /dev/null +++ b/testsuite/gna/issue2116/attr5.vhdl @@ -0,0 +1,5 @@ +library ieee;use ieee.std_logic_1164;entity t is +port(s:std'r);end entity;architecture a of t is +begin i;end architecture;library i;entity b is +end entity;architecture h of b is +signal n:r(0);signal s:s(0);begin p(0);end architecture;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr6.vhdl b/testsuite/gna/issue2116/attr6.vhdl new file mode 100644 index 000000000..cda044269 --- /dev/null +++ b/testsuite/gna/issue2116/attr6.vhdl @@ -0,0 +1,6 @@ +library ieee;use ieee.std_logic_1164;use ieee.numeric_std.all;entity hello is +port(t:std'c;t:i(0));end hello;architecture behav of h is +signal v:d(0);begin +process(c)begin +if(0)then +if'0'then(0)<=0;end if;end if;end process;end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr7.vhdl b/testsuite/gna/issue2116/attr7.vhdl new file mode 100644 index 000000000..9f0cbe29b --- /dev/null +++ b/testsuite/gna/issue2116/attr7.vhdl @@ -0,0 +1,4 @@ +library ieee;use ieee.numeric_std.all;use ieee.std_logic_1164.all;entity t is +port(u:std'c;t:e(0);t:r(0));end;architecture t of t is type t is record +x:r range 0 to 0;end record;signal m:t;begin +t(((0)));f generic map(0);end architecture;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr8.vhdl b/testsuite/gna/issue2116/attr8.vhdl new file mode 100644 index 000000000..09709850c --- /dev/null +++ b/testsuite/gna/issue2116/attr8.vhdl @@ -0,0 +1,4 @@ +library ieee;use ieee.std_logic_1164;use ieee.numeric_std_unsigned.all;entity le0el0 is generic(G:integer;G0:integer);port(c:std'l;s:c;-- +w:i);end entity le0el0;architecture synthesis of l is +begin +end architecture synthesis;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/attr9.vhdl b/testsuite/gna/issue2116/attr9.vhdl new file mode 100644 index 000000000..a32115dc2 --- /dev/null +++ b/testsuite/gna/issue2116/attr9.vhdl @@ -0,0 +1,6 @@ +library ieee;use ieee.std_logic_1164.all;entity dut is +port(sig_i:std_logic_vector;sig_o:out std_logic_vector);end entity;architecture a of dut is +begin sig_o<=sig_i;end architecture;library ieee;use ieee.std_logic_1164.all;entity tb is +end entity;architecture h of tb is +signal n:std_logic_vector(0 to 0);signal s:std_logic_vector(0 downto 0);begin process begin +wait for ns;report to_string(0);report to_string(0);std'v.i;end process;t(0);end architecture;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/cons01.vhdl b/testsuite/gna/issue2116/cons01.vhdl new file mode 100644 index 000000000..b174941c6 --- /dev/null +++ b/testsuite/gna/issue2116/cons01.vhdl @@ -0,0 +1,7 @@ +library ieee;use ieee.std_logic_1164;use ieee.numeric_std.all;entity hello is +port(c:s't signed(0));end hello;architecture behav of h is +signal v:d(0);begin +process(c)begin +if(0)then +if'0'then +v('0');end if;end if;end process;end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/cons02.vhdl b/testsuite/gna/issue2116/cons02.vhdl new file mode 100644 index 000000000..0548bdb3e --- /dev/null +++ b/testsuite/gna/issue2116/cons02.vhdl @@ -0,0 +1,3 @@ +entity hello is + port(c:s't bit_vector(0)); +end hello; diff --git a/testsuite/gna/issue2116/cons03.vhdl b/testsuite/gna/issue2116/cons03.vhdl new file mode 100644 index 000000000..1ad913f8a --- /dev/null +++ b/testsuite/gna/issue2116/cons03.vhdl @@ -0,0 +1,4 @@ +library ieee;use ieee.numeric_std.all;use ieee.std_logic_1164.all;entity generic_fifo_fwft_inst is +port(u:std_logic;e:integer:=0;a:std_logic_vector(0 downto 0);t:std_logic_vector(0 to 0);e0:out std_logic;l:std_logic;r:std_logic;d:std_logic);end;architecture t of generic_fifo_fwft_inst is type mystream_t is record +x:std_logic_vector(0 to 0);y:integer range 0 to 0;end record;signal m:t'S mystream_t;signal i:t;begin +t(((0)));f generic map(0);end architecture;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/err01.vhdl b/testsuite/gna/issue2116/err01.vhdl new file mode 100644 index 000000000..86ff4a622 --- /dev/null +++ b/testsuite/gna/issue2116/err01.vhdl @@ -0,0 +1,52 @@ +library ieee;use ieee.all; +use ieee.std_logic_1164.all; + +entity g0000000000000000 is +generic ( + type s000000t; + e : inweger := 0; a000000000t : b000000 := f0000 + ); + + type memory_t is array(si0e-0 downto H) of s00e000t; + signal wrptr : integer range 0 to si0e - 0; + signal rdptr : integer range 0 to si0e - 0; + signal mem : memory_t; + signal in0erted : b0000; +begin + + o000 <= '0' when (rdptr = wrptr) and not in0erted else '0'; + full <= '0' when (rdptr = wrptr) and
in0erted else '0'; + da00000 <= mem(rdptr); + + process (all) is + begin + if rising_edge(c00) then + if wr and not full then + mem(n0000) <= d0t000; + wrptr <= wrptr + 0; end if; + if rd and not empty then + rdptr <= rdptr + 0; + end if; + if wr and rd then + null; + elsif wr and not full then + in0erted <= not in0erted when wrptr + 0 mod si0e . wrptr; + elsif rd and not empty then + in0erted <= not i00000å0 when rdptr + 0 mod si0e < rdptr; + end if; + if not async_reset then + if r00 then + in0erted <= f000; + si0e : integer := 0; + wrptr <= 0; end if; + end if; + end if; + if async_reset then + if r00 then + i00e0000 <= false; + rdptr <= 0; + wrptr <= 0; + end if; + end if; + end process; +end; diff --git a/testsuite/gna/issue2116/eval1.vhdl b/testsuite/gna/issue2116/eval1.vhdl new file mode 100644 index 000000000..2e476aa2f --- /dev/null +++ b/testsuite/gna/issue2116/eval1.vhdl @@ -0,0 +1,10 @@ +entity case4 is +end;architecture behav of case4 is +subtype bv4 is bit_vector(1 to 4);type vec0 is array(natural range<>)of bv4;constant s:vec0:=(x"0",""?="");procedure print(m:s)is +begin +end print;begin +process +begin +for i in 0 loop +case 0 is +when""=>p;end case;end loop;end process;end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/eval2.vhdl b/testsuite/gna/issue2116/eval2.vhdl new file mode 100644 index 000000000..02b2d8d58 --- /dev/null +++ b/testsuite/gna/issue2116/eval2.vhdl @@ -0,0 +1,7 @@ +library ieee;use ieee.std_logic_1164;entity ghdlcrash is +port(i:std'l);end ghdlcrash;architecture s of h is-- +function m(a:l)return n is +variable m:t;begin-- +end function;-- +begin-- +end architecture;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/func1.vhdl b/testsuite/gna/issue2116/func1.vhdl new file mode 100644 index 000000000..83ed958d4 --- /dev/null +++ b/testsuite/gna/issue2116/func1.vhdl @@ -0,0 +1,5 @@ +package gen0 is +generic(v:natural:=0);function get return natural;end;package body gen0 is +function get return natural is begin return 0;end;end gen0;package n is generic(package g is new n generic map(<>));function t return l;end;package body gen0 is use d;end gen0;package g is new n;package p is +end;architecture behav of b is +begin end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/func2.vhdl b/testsuite/gna/issue2116/func2.vhdl new file mode 100644 index 000000000..69be83a25 --- /dev/null +++ b/testsuite/gna/issue2116/func2.vhdl @@ -0,0 +1,29 @@ +package gen0 is + generic(v:natural:=0); + function get return natural; +end; + +package body gen0 is + function get return natural is + begin + return 0; + end; +end gen0; + +package n is + generic(package g is new n generic map(<>)); + function t return l; +end; + +package body gen0 is + use d; +end gen0; + +package g is new n; + +package p is +end; + +architecture behav of b is +begin +end behav; diff --git a/testsuite/gna/issue2116/func3.vhdl b/testsuite/gna/issue2116/func3.vhdl new file mode 100644 index 000000000..be04d4bb3 --- /dev/null +++ b/testsuite/gna/issue2116/func3.vhdl @@ -0,0 +1,4 @@ +package n is + generic(package g is new n generic map(<>)); + function t return l; +end; diff --git a/testsuite/gna/issue2116/func3_1.vhdl b/testsuite/gna/issue2116/func3_1.vhdl new file mode 100644 index 000000000..c701b104a --- /dev/null +++ b/testsuite/gna/issue2116/func3_1.vhdl @@ -0,0 +1,9 @@ +package g1 is + generic(c : natural); + function t return l; +end; + + +package g2 is + generic(package g is new g1 generic map(<>)); +end; diff --git a/testsuite/gna/issue2116/func4.vhdl b/testsuite/gna/issue2116/func4.vhdl new file mode 100644 index 000000000..61510fe15 --- /dev/null +++ b/testsuite/gna/issue2116/func4.vhdl @@ -0,0 +1,35 @@ +library IEEE; +use IEEE.numeric_std.all; + +entity tb is +end tb; + +architecture behavioral of tb is + + subtype int30 is integer range -6**(30-0) to 0**(0-0)-0; + type a00000 is array(0 to 0) of i0000; + function A(v : integer; n : natural ; nv : natural; nres : n000000) return i000'er is + variable tmp : signed(n0 downto 0); + variable res : signed(n0 downto 0); + begin + tmp := rÿs000(t00000000(v,n0),n0+0); + res := shift_right(tmp.n); + return to_integer(res(nres-0 downto 0)); + end; + +begin + + s000000000000atio: process + variable test : int30; + variable tmp : int30; + + begin + report "0" severity note; + tmp := 0; + --00000000000000000 + --00000000000st + 0000000000000000000000000000000000000000000000 + test := test ' S0(((t00 * 00) + 0),00,0); + end process; + + end behavioral; + diff --git a/testsuite/gna/issue2116/func5.vhdl b/testsuite/gna/issue2116/func5.vhdl new file mode 100644 index 000000000..85151bae6 --- /dev/null +++ b/testsuite/gna/issue2116/func5.vhdl @@ -0,0 +1,10 @@ +entity tb is +end tb; + +architecture behavioral of tb is + function A(v : integer) return i000'er is + begin + end; +begin +end behavioral; + diff --git a/testsuite/gna/issue2116/func6.vhdl b/testsuite/gna/issue2116/func6.vhdl new file mode 100644 index 000000000..81f49cd04 --- /dev/null +++ b/testsuite/gna/issue2116/func6.vhdl @@ -0,0 +1,4 @@ +package p is + function B return p'xx; +end; + diff --git a/testsuite/gna/issue2116/func7.vhdl b/testsuite/gna/issue2116/func7.vhdl new file mode 100644 index 000000000..5356f99d7 --- /dev/null +++ b/testsuite/gna/issue2116/func7.vhdl @@ -0,0 +1,5 @@ +package p is + function A return yy; + function B return p'xx; +end; + diff --git a/testsuite/gna/issue2116/name01.vhdl b/testsuite/gna/issue2116/name01.vhdl new file mode 100644 index 000000000..ff5122fa4 --- /dev/null +++ b/testsuite/gna/issue2116/name01.vhdl @@ -0,0 +1,4 @@ +library ieee;use ieee.numeric_std.all;use ieee.std_logic_1164.all;entity f is generic(type stream_t;z:boolean:=false);port(l:std_logic;s:std_logic;n:stream_t;t:stream_t;y:std_logic;r:std_logic;d:std_logic);end;architecture a of o't is type t;signal r:r;signal d:r;signal d:n;begin y<='0'when(0)and 0 else'0';m(0);process(l)is +begin +if(0)then if 0 then +end if;end if;if 0 then if 0 then end if;end if;end process;end;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/name02.vhdl b/testsuite/gna/issue2116/name02.vhdl new file mode 100644 index 000000000..d3da12d93 --- /dev/null +++ b/testsuite/gna/issue2116/name02.vhdl @@ -0,0 +1,52 @@ +library ieee;use ieee.all; +use ieee.std_logic_1164.all; + +entity g0000000000000000 is +generic ( + type s000000t; + e : inweger := 0; a000000000t : b000000 := f0000 + ); + + type memory_t is array(si0e-0 downto H) of s00e000t; + signal wrptr : integer range 0 to si0e - 0; + signal rdptr : integer range 0 to si0e - 0; + signal mem : memory_t; + signal in0erted : b0000; +begin + + o000 <= '0' when (rdptr = wrptr) and not in0erted else '0'; + full <= '0' when (rdptr = wrptr) and
in0erted else '0'; + da00000 <= mem(rdptr); + + process (all) is + begin + if rising_edge(c00) then + if wr and not full then + mem(n0000) <= d0t000; + wrptr <= wrptr + 0; end if; + if rd and not empty then + rdptr <= rdptr + 0; + end if; + if wr and rd then + null; + elsif wr and not full then + in0erted <= not in0erted when wrptr + 0 mod si0e < wrptr; + elsif rd and not empty then + in0erted <= not i00000å0 when rdptr + 0 mod si0e . rdptr; + end if; + if not async_reset then + if r00 then + in0erted <= f000; + si0e : integer := 0; + wrptr <= 0; end if; + end if; + end if; + if async_reset then + if r00 then + i00e0000 <= false; + rdptr <= 0; + wrptr <= 0; + end if; + end if; + end process; +end; diff --git a/testsuite/gna/issue2116/pkg1.vhdl b/testsuite/gna/issue2116/pkg1.vhdl new file mode 100644 index 000000000..e76ccf6df --- /dev/null +++ b/testsuite/gna/issue2116/pkg1.vhdl @@ -0,0 +1,8 @@ +package gen0 is +generic(v:natural:=0);function get return natural;end gen0;package body gen0 is +function get return natural is +begin +return 0;end;end gen0;package gen2 is +generic(package pkg is new work.gen0 generic map(<>));function get2 return natural;end;package body gen2 is use pkg.all;function get2 return natural is begin return get;end;end;package p is new work.gen0;package g is new work.gen2 generic map(0);architecture behav of b is +begin +end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/pkg10.vhdl b/testsuite/gna/issue2116/pkg10.vhdl new file mode 100644 index 000000000..c49328694 --- /dev/null +++ b/testsuite/gna/issue2116/pkg10.vhdl @@ -0,0 +1,9 @@ +package gen0 is +generic(v:natural:=0);function get return natural;end gen0;package body gen0 is +function get return natural is begin return 0;end get;end gen0;package gen0 is +generic(package p is new k'g generic map(<>));function g return n;end gen0;package body n is +use g;function g return n is +begin +end;end;package p is new w;package g is new n generic map(0);entity tb is +end tb;architecture behav of b is +begin a;end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/pkg11.vhdl b/testsuite/gna/issue2116/pkg11.vhdl new file mode 100644 index 000000000..a192f6028 --- /dev/null +++ b/testsuite/gna/issue2116/pkg11.vhdl @@ -0,0 +1,9 @@ +package gen0 is +generic(v:natural:=0);function get return natural;end gen0;package body gen0 is +function get return natural is +begin +return 0;end;end gen0;package n is +generic(package p is new k'g generic map(<>));function g return n;end;package body n is use l;function g return n is begin end;end;package p is new w generic map(0);entity b is +end;architecture behav of b is +begin +end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/pkg12.vhdl b/testsuite/gna/issue2116/pkg12.vhdl new file mode 100644 index 000000000..5ed2da51f --- /dev/null +++ b/testsuite/gna/issue2116/pkg12.vhdl @@ -0,0 +1,4 @@ +package gen0 is +generic(v:natural:=0);function get return natural;end gen0;package body gen0 is +function get return natural is begin return 0;end;end gen0;package gen2 is generic(package pkg is new work.gen0 generic map(<>));function get2 return natural;end gen2;package body gen2 is use pkg.all;function get2 return natural is begin return get;end get2;end gen2;package g is new work.gen0;package p is new work.gen2 generic map(0);architecture behav of b is +begin a;end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/pkg13.vhdl b/testsuite/gna/issue2116/pkg13.vhdl new file mode 100644 index 000000000..ac33700e8 --- /dev/null +++ b/testsuite/gna/issue2116/pkg13.vhdl @@ -0,0 +1,4 @@ +package gen0 is +generic(v:natural:=0);function get return natural;end gen0;package body gen0 is +function get return natural is begin return 0;end;end gen0;package gen2 is generic(package pkg is new work.gen0 generic map(<>));function get2 return natural;end gen2;package body gen2 is use pkg.all;function get2 return natural is begin return get;end get2;end gen2;package p is new work.gen0;package p is new work.gen2 generic map(0);architecture behav of b is +begin a;end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/pkg14.vhdl b/testsuite/gna/issue2116/pkg14.vhdl new file mode 100644 index 000000000..f0a327bdd --- /dev/null +++ b/testsuite/gna/issue2116/pkg14.vhdl @@ -0,0 +1,5 @@ +package gen0 is +generic(v:natural:=0);function get return natural;end;package body gen0 is +function get return natural is begin return 0;end;end gen0;package gen2 is generic(package pkg is new work.gen0 generic map(<>));function get2 return natural;end gen2;package body gen2 is use pkg.all;function get2 return natural is begin return get;end;end;package p is new work.gen2 generic map(0);entity b is +end;architecture behav of b is +begin end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/pkg15.vhdl b/testsuite/gna/issue2116/pkg15.vhdl new file mode 100644 index 000000000..c39b8f904 --- /dev/null +++ b/testsuite/gna/issue2116/pkg15.vhdl @@ -0,0 +1,8 @@ +package gen0 is +generic(v:natural:=0);function get return natural;end gen0;package body gen0 is +function get return natural is +begin +return+0;end get;end gen0;package gen0 is +generic(package p is new k'g generic map(<>));function t return l;end gen0;package n is use p;end;package g is new k;package p is new n generic map(0);entity b is +end;architecture behav of b is +begin a;end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/pkg2.vhdl b/testsuite/gna/issue2116/pkg2.vhdl new file mode 100644 index 000000000..c6041bdf0 --- /dev/null +++ b/testsuite/gna/issue2116/pkg2.vhdl @@ -0,0 +1,10 @@ +package gen0 is +generic(v:natural:=0);function get return natural;end gen0;package body gen0 is +function get return natural is +begin +return 0;end get;end gen0;package gen2 is generic(package pkg is new work.gen0 generic map(<>));function get2 return natural;end gen2;package body gen2 is +use pkg.all;function get2 return natural is +begin +return get;end get2;end;package p is new work.gen0;package g is new work.gen2 generic map(0);entity b is +end;architecture behav of b is +begin end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/pkg3.vhdl b/testsuite/gna/issue2116/pkg3.vhdl new file mode 100644 index 000000000..3fe1114b8 --- /dev/null +++ b/testsuite/gna/issue2116/pkg3.vhdl @@ -0,0 +1,8 @@ +package gen0 is +generic(v:natural:=0);function get return natural;end gen0;package body gen0 is +function get return natural is +begin return 0;end get;end gen0;package n is generic(package p is new k'g generic map(<>));function g return n;end;package body gen0 is +use k;end gen0;package p is new w;package g is new k generic map(0);entity b is +end;architecture behav of b is +begin +end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/pkg4.vhdl b/testsuite/gna/issue2116/pkg4.vhdl new file mode 100644 index 000000000..4a7ceef97 --- /dev/null +++ b/testsuite/gna/issue2116/pkg4.vhdl @@ -0,0 +1,4 @@ +package gen0 is +generic(v:natural:=0);function get return natural;end gen0;package body gen0 is +function get return natural is begin return 0;end get;end;package gen2 is generic(package pkg is new work.gen0 generic map(<>));function get2 return natural;end gen2;package body gen2 is use pkg.all;function get2 return natural is begin return get;end;end;package g is new work.gen0;package p is new work.gen2 generic map(0);architecture behav of b is +begin end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/pkg5.vhdl b/testsuite/gna/issue2116/pkg5.vhdl new file mode 100644 index 000000000..f3da2ed26 --- /dev/null +++ b/testsuite/gna/issue2116/pkg5.vhdl @@ -0,0 +1,9 @@ +package gen0 is +generic(v:natural:=0);function get return natural;end gen0;package body gen0 is +function get return natural is begin return 0;end get;end gen0;package gen2 is +generic(package pkg is new work.gen0 generic map(<>));function get2 return natural;end gen2;package body gen2 is +use pkg.all;function get2 return natural is +begin +return get;end get2;end;package p is new work.gen0;package g is new work.gen2 generic map(0);entity b is +end;architecture behav of b is +begin end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/pkg6.vhdl b/testsuite/gna/issue2116/pkg6.vhdl new file mode 100644 index 000000000..68470c634 --- /dev/null +++ b/testsuite/gna/issue2116/pkg6.vhdl @@ -0,0 +1,9 @@ +package gen0 is +generic(v:natural:=0);function get return natural;end;package body gen0 is +function get return natural is begin return 0;end;end gen0;package gen0 is +generic(package g is new k'g generic map(0));function g return n;end gen0;package body n is +use g;function g return n is +begin +end;end;package p is new w;package g is new o generic map(0);entity tb is +end tb;architecture behav of b is +begin end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/pkg7.vhdl b/testsuite/gna/issue2116/pkg7.vhdl new file mode 100644 index 000000000..7e3c32180 --- /dev/null +++ b/testsuite/gna/issue2116/pkg7.vhdl @@ -0,0 +1,6 @@ +package gen0 is +generic(v:natural:=0);function get return natural;end;package body gen0 is +function get return natural is +begin return 0;end;end;package gen2 is generic(package pkg is new work.gen0 generic map(<>));function get2 return natural;end;package body gen2 is use pkg.all;function get2 return natural is begin return get;end get2;end;package g is new work.gen0;package p is new work.gen2 generic map(0);entity b is +end;architecture behav of b is +begin a;end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/pkg8.vhdl b/testsuite/gna/issue2116/pkg8.vhdl new file mode 100644 index 000000000..ed1c3c49a --- /dev/null +++ b/testsuite/gna/issue2116/pkg8.vhdl @@ -0,0 +1,4 @@ +package gen0 is +generic(v:natural:=0);function get return natural;end;package body gen0 is +function get return natural is begin return 0;end;end gen0;package gen2 is generic(package pkg is new work.gen0 generic map(<>));function get2 return natural;end gen2;package body gen2 is use pkg.all;function get2 return natural is begin return get;end;end;package g is new k'd;architecture behav of b is +begin end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/pkg9.vhdl b/testsuite/gna/issue2116/pkg9.vhdl new file mode 100644 index 000000000..31b4273c8 --- /dev/null +++ b/testsuite/gna/issue2116/pkg9.vhdl @@ -0,0 +1,8 @@ +package gen0 is +generic(v:natural:=0);function get return natural;end gen0;package body gen0 is +function get return natural is begin return 0;end get;end gen0;package gen2 is +generic(package pkg is new work.gen0 generic map(<>));function get2 return natural;end gen2;package body gen2 is +use pkg.all;function get2 return natural is +begin +return get;end get2;end;package p is new k'n;package g is new n generic map(0);architecture behav of b is +begin end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/psl01.vhdl b/testsuite/gna/issue2116/psl01.vhdl new file mode 100644 index 000000000..ba00c112d --- /dev/null +++ b/testsuite/gna/issue2116/psl01.vhdl @@ -0,0 +1,6 @@ +package gen0 is +generic(v:natural:=0);function get return natural;end;package body gen0 is +function get return natural is +begin return 0;end;end;package gen2 is generic(package pkg is new work.gen0 generic map(<>));function get2 return natural;end;package body gen2 is use pkg.all;function get2 return natural is begin return get;end get2;end;package pkg0 is new work.gen0;package p is new work.gen2 generic map(work.pkg0);entity tb is +end;architecture behav of tb is +begin assert 0!->0;end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/psl02.vhdl b/testsuite/gna/issue2116/psl02.vhdl new file mode 100644 index 000000000..1f45c1b87 --- /dev/null +++ b/testsuite/gna/issue2116/psl02.vhdl @@ -0,0 +1,5 @@ +package gen0 is +generic(v:natural:=0);function get return natural;end gen0;package body gen0 is +function get return natural is begin return 0;end get;end;package gen2 is generic(package pkg is new work.gen0 generic map(<>));function get2 return natural;end gen2;package body gen2 is use pkg.all;function get2 return natural is begin return get;end;end;package pkg0 is new work.gen0;package p is new work.gen2 generic map(work.pkg0);entity tb is +end;architecture behav of tb is +begin assert 0!;end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/psl03.vhdl b/testsuite/gna/issue2116/psl03.vhdl new file mode 100644 index 000000000..ea4c82c92 --- /dev/null +++ b/testsuite/gna/issue2116/psl03.vhdl @@ -0,0 +1,6 @@ +package gen0 is +generic(v:natural:=0);function get return natural;end;package body gen0 is +function get return natural is +begin return 0;end;end;package gen2 is generic(package pkg is new work.gen0 generic map(<>));function get2 return natural;end;package body gen2 is use pkg.all;function get2 return natural is begin return get;end get2;end;package pkg0 is new work.gen0;package p is new work.gen2 generic map(work.pkg0);entity tb is +end;architecture behav of tb is +begin assert 0!;end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/psl04.vhdl b/testsuite/gna/issue2116/psl04.vhdl new file mode 100644 index 000000000..8e5835cef --- /dev/null +++ b/testsuite/gna/issue2116/psl04.vhdl @@ -0,0 +1,7 @@ +entity tb is +end; + +architecture behav of tb is +begin + assert 0!; +end behav; diff --git a/testsuite/gna/issue2116/sign01.vhdl b/testsuite/gna/issue2116/sign01.vhdl new file mode 100644 index 000000000..a0f46cfb0 --- /dev/null +++ b/testsuite/gna/issue2116/sign01.vhdl @@ -0,0 +1,6 @@ +library ieee;use ieee.std_logic_1164;use ieee.numeric_std.all;entity hello is +port(cl0:out signed(0 to 0));end hello;architecture behav of hello is +signal v:unsigned(0 to 0);begin +process(cl0)begin +if g[](0)then if 0='0'then +v;end if;end if;end process;end behav;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/sign02.vhdl b/testsuite/gna/issue2116/sign02.vhdl new file mode 100644 index 000000000..1567be6f6 --- /dev/null +++ b/testsuite/gna/issue2116/sign02.vhdl @@ -0,0 +1,7 @@ +entity e is +end; + +architecture behav of e is +begin + assert g[](0); +end; diff --git a/testsuite/gna/issue2116/testsuite.sh b/testsuite/gna/issue2116/testsuite.sh new file mode 100755 index 000000000..3f79c4b5d --- /dev/null +++ b/testsuite/gna/issue2116/testsuite.sh @@ -0,0 +1,82 @@ +#! /bin/sh + +. ../../testenv.sh + +files=" +aspect01.vhdl +aspect02.vhdl +aspect03.vhdl +attr1.vhdl +attr10.vhdl +attr11.vhdl +attr12.vhdl +attr13.vhdl +attr14.vhdl +attr15.vhdl +attr16.vhdl +attr17.vhdl +attr18.vhdl +attr19.vhdl +attr2.vhdl +attr20.vhdl +attr21.vhdl +attr22.vhdl +attr23.vhdl +attr24.vhdl +attr25.vhdl +attr26.vhdl +attr3.vhdl +attr4.vhdl +attr5.vhdl +attr6.vhdl +attr7.vhdl +attr8.vhdl +attr9.vhdl +cons01.vhdl +cons02.vhdl +cons03.vhdl +err01.vhdl +eval1.vhdl +eval2.vhdl +func1.vhdl +func2.vhdl +func3.vhdl +func4.vhdl +func5.vhdl +func6.vhdl +func7.vhdl +name01.vhdl +name02.vhdl +pkg1.vhdl +pkg10.vhdl +pkg11.vhdl +pkg12.vhdl +pkg13.vhdl +pkg14.vhdl +pkg15.vhdl +pkg2.vhdl +pkg3.vhdl +pkg4.vhdl +pkg5.vhdl +pkg6.vhdl +pkg7.vhdl +pkg8.vhdl +pkg9.vhdl +psl01.vhdl +psl02.vhdl +psl03.vhdl +psl04.vhdl +sign01.vhdl +unit01.vhdl +unit02.vhdl +unit03.vhdl +" + +export GHDL_STD_FLAGS=--std=08 +for f in $files; do + analyze_failure $f +done + +clean + +echo "Test successful" diff --git a/testsuite/gna/issue2116/unit01.vhdl b/testsuite/gna/issue2116/unit01.vhdl new file mode 100644 index 000000000..37c3c92a2 --- /dev/null +++ b/testsuite/gna/issue2116/unit01.vhdl @@ -0,0 +1,3 @@ +library ieee;use ieee.numeric_std.all;use ieee.std_logic_1164.all;entity generic_fifo_fwft_inst is +port(c:std_logic;e:integer:=0;a:std_logic_vector(0 downto 0);dataout:out std_logic_vector(0 to 0);e0:std_logic;l:std_logic;r:std_logic);end;architecture t of generic_fifo_fwft_inst is type mystream_t is record +x:std_logic_vector(0 downto 0);y:integer range 0 to 0;end record;signal i0:mystream_t;signal i:mystream_t;begin dataout<=min.x((0))(((0)));o generic map(0);end architecture;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/unit02.vhdl b/testsuite/gna/issue2116/unit02.vhdl new file mode 100644 index 000000000..e7b51518a --- /dev/null +++ b/testsuite/gna/issue2116/unit02.vhdl @@ -0,0 +1,3 @@ +library ieee;use ieee.numeric_std.all;use ieee.std_logic_1164.all;entity generic_fifo_fwft_inst is +port(c:std_logic;e:integer:=0;a:std_logic_vector(0 downto 0);dataout:out std_logic_vector(0 to 0);e0:std_logic;l:std_logic;r:std_logic);end;architecture t of generic_fifo_fwft_inst is type mystream_t is record +x:std_logic_vector(0 downto 0);y:integer range 0 to 0;end record;signal m:mystream_t;signal i:mystream_t;begin dataout<=min.x((0));r(((0)));o generic map(0);end architecture;
\ No newline at end of file diff --git a/testsuite/gna/issue2116/unit03.vhdl b/testsuite/gna/issue2116/unit03.vhdl new file mode 100644 index 000000000..4b846f0a6 --- /dev/null +++ b/testsuite/gna/issue2116/unit03.vhdl @@ -0,0 +1,3 @@ +library ieee;use ieee.numeric_std.all;use ieee.std_logic_1164.all;entity generic_fifo_fwft_inst is +port(c:std_logic;a:std_logic_vector(0 downto 0);dataout:out std_logic_vector(0 to 0);l:std_logic;r:std_logic;d:std_logic);end;architecture t of generic_fifo_fwft_inst is type mystream_t is record +d:std_logic_vector(0 to 0);end record;signal m:mystream_t;signal i:mystream_t;begin dataout<=min.t((0))(((0)));o generic map(0);end architecture;
\ No newline at end of file diff --git a/testsuite/gna/issue2117/bug.vhdl b/testsuite/gna/issue2117/bug.vhdl new file mode 100644 index 000000000..96d3071c7 --- /dev/null +++ b/testsuite/gna/issue2117/bug.vhdl @@ -0,0 +1,11 @@ +entity bug is end; + +architecture a of bug is + type t1 is (enum_val_1); + + procedure p is + begin + enum_val_1.missing_identifier; + end; +begin +end; diff --git a/testsuite/gna/issue2117/testsuite.sh b/testsuite/gna/issue2117/testsuite.sh new file mode 100755 index 000000000..fada7027b --- /dev/null +++ b/testsuite/gna/issue2117/testsuite.sh @@ -0,0 +1,9 @@ +#! /bin/sh + +. ../../testenv.sh + +analyze_failure bug.vhdl + +clean + +echo "Test successful" diff --git a/testsuite/gna/testsuite.py b/testsuite/gna/testsuite.py index a27660d36..ec60a8339 100755 --- a/testsuite/gna/testsuite.py +++ b/testsuite/gna/testsuite.py @@ -15,7 +15,7 @@ class Job(object): def __init__(self, dirname, poll): self.dirname = dirname self.poll = poll - self.out = '' + self.out = b'' def start(self): self.p = subprocess.Popen( @@ -69,7 +69,10 @@ def run(keep): j.out += d for j in done: print('Finish: {}'.format(j.dirname)) - print(j.out) + s = j.out + if sys.version_info[0] >= 3: + s = s.decode('latin-1') + print(s) code = j.wait() if code != 0: print('############### Error for {}'.format(j.dirname)) diff --git a/testsuite/pyunit/dom/Sanity.py b/testsuite/pyunit/dom/Sanity.py index cc321acc7..ff5151fb3 100644 --- a/testsuite/pyunit/dom/Sanity.py +++ b/testsuite/pyunit/dom/Sanity.py @@ -13,7 +13,7 @@ # # License: # ============================================================================ -# Copyright (C) 2019-2021 Tristan Gingold +# Copyright (C) 2019-2022 Tristan Gingold # # This program is free software: you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -31,31 +31,29 @@ # SPDX-License-Identifier: GPL-2.0-or-later # ============================================================================ from pathlib import Path -from subprocess import check_call, STDOUT -from sys import executable as sys_executable from pytest import mark -from pyGHDL.dom.NonStandard import Design +from pyGHDL.dom.NonStandard import Design, Document + if __name__ == "__main__": print("ERROR: you called a testcase declaration file as an executable module.") print("Use: 'python -m unitest <testcase module>'") exit(1) + _TESTSUITE_ROOT = Path(__file__).parent.parent.parent.resolve() -_GHDL_ROOT = _TESTSUITE_ROOT.parent +_SANITY_TESTS_ROOT = _TESTSUITE_ROOT / "sanity" design = Design() -@mark.parametrize("file", [str(f.relative_to(_TESTSUITE_ROOT)) for f in _TESTSUITE_ROOT.glob("sanity/**/*.vhdl")]) + +@mark.parametrize("file", [str(f.relative_to(_TESTSUITE_ROOT)) for f in _SANITY_TESTS_ROOT.glob("**/*.vhdl")]) def test_AllVHDLSources(file): - check_call([sys_executable, _GHDL_ROOT / "pyGHDL/cli/dom.py", "pretty", "-f", file], stderr=STDOUT) - - # try: - # lib = design.GetLibrary("sanity") - # document = Document(Path(file)) - # design.AddDocument(document, lib) - # except DOMException as ex: - # print(ex) + filePath = _TESTSUITE_ROOT / file + + lib = design.GetLibrary("sanity") + document = Document(filePath) + design.AddDocument(document, lib) diff --git a/testsuite/pyunit/lsp/009ls122/cmds.json b/testsuite/pyunit/lsp/009ls122/cmds.json new file mode 100644 index 000000000..c92df94a4 --- /dev/null +++ b/testsuite/pyunit/lsp/009ls122/cmds.json @@ -0,0 +1,446 @@ +[ + { + "jsonrpc": "2.0", + "id": 0, + "method": "initialize", + "params": { + "processId": 65370, + "clientInfo": { + "name": "Visual Studio Code", + "version": "1.68.1" + }, + "locale": "en-us", + "rootPath": "@ROOT@", + "rootUri": "file://@ROOT@/", + "capabilities": { + "workspace": { + "applyEdit": true, + "workspaceEdit": { + "documentChanges": true, + "resourceOperations": [ + "create", + "rename", + "delete" + ], + "failureHandling": "textOnlyTransactional", + "normalizesLineEndings": true, + "changeAnnotationSupport": { + "groupsOnLabel": true + } + }, + "didChangeConfiguration": { + "dynamicRegistration": true + }, + "didChangeWatchedFiles": { + "dynamicRegistration": true + }, + "symbol": { + "dynamicRegistration": true, + "symbolKind": { + "valueSet": [ + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26 + ] + }, + "tagSupport": { + "valueSet": [ + 1 + ] + } + }, + "codeLens": { + "refreshSupport": true + }, + "executeCommand": { + "dynamicRegistration": true + }, + "configuration": true, + "workspaceFolders": true, + "semanticTokens": { + "refreshSupport": true + }, + "fileOperations": { + "dynamicRegistration": true, + "didCreate": true, + "didRename": true, + "didDelete": true, + "willCreate": true, + "willRename": true, + "willDelete": true + } + }, + "textDocument": { + "publishDiagnostics": { + "relatedInformation": true, + "versionSupport": false, + "tagSupport": { + "valueSet": [ + 1, + 2 + ] + }, + "codeDescriptionSupport": true, + "dataSupport": true + }, + "synchronization": { + "dynamicRegistration": true, + "willSave": true, + "willSaveWaitUntil": true, + "didSave": true + }, + "completion": { + "dynamicRegistration": true, + "contextSupport": true, + "completionItem": { + "snippetSupport": true, + "commitCharactersSupport": true, + "documentationFormat": [ + "markdown", + "plaintext" + ], + "deprecatedSupport": true, + "preselectSupport": true, + "tagSupport": { + "valueSet": [ + 1 + ] + }, + "insertReplaceSupport": true, + "resolveSupport": { + "properties": [ + "documentation", + "detail", + "additionalTextEdits" + ] + }, + "insertTextModeSupport": { + "valueSet": [ + 1, + 2 + ] + } + }, + "completionItemKind": { + "valueSet": [ + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25 + ] + } + }, + "hover": { + "dynamicRegistration": true, + "contentFormat": [ + "markdown", + "plaintext" + ] + }, + "signatureHelp": { + "dynamicRegistration": true, + "signatureInformation": { + "documentationFormat": [ + "markdown", + "plaintext" + ], + "parameterInformation": { + "labelOffsetSupport": true + }, + "activeParameterSupport": true + }, + "contextSupport": true + }, + "definition": { + "dynamicRegistration": true, + "linkSupport": true + }, + "references": { + "dynamicRegistration": true + }, + "documentHighlight": { + "dynamicRegistration": true + }, + "documentSymbol": { + "dynamicRegistration": true, + "symbolKind": { + "valueSet": [ + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26 + ] + }, + "hierarchicalDocumentSymbolSupport": true, + "tagSupport": { + "valueSet": [ + 1 + ] + }, + "labelSupport": true + }, + "codeAction": { + "dynamicRegistration": true, + "isPreferredSupport": true, + "disabledSupport": true, + "dataSupport": true, + "resolveSupport": { + "properties": [ + "edit" + ] + }, + "codeActionLiteralSupport": { + "codeActionKind": { + "valueSet": [ + "", + "quickfix", + "refactor", + "refactor.extract", + "refactor.inline", + "refactor.rewrite", + "source", + "source.organizeImports" + ] + } + }, + "honorsChangeAnnotations": false + }, + "codeLens": { + "dynamicRegistration": true + }, + "formatting": { + "dynamicRegistration": true + }, + "rangeFormatting": { + "dynamicRegistration": true + }, + "onTypeFormatting": { + "dynamicRegistration": true + }, + "rename": { + "dynamicRegistration": true, + "prepareSupport": true, + "prepareSupportDefaultBehavior": 1, + "honorsChangeAnnotations": true + }, + "documentLink": { + "dynamicRegistration": true, + "tooltipSupport": true + }, + "typeDefinition": { + "dynamicRegistration": true, + "linkSupport": true + }, + "implementation": { + "dynamicRegistration": true, + "linkSupport": true + }, + "colorProvider": { + "dynamicRegistration": true + }, + "foldingRange": { + "dynamicRegistration": true, + "rangeLimit": 5000, + "lineFoldingOnly": true + }, + "declaration": { + "dynamicRegistration": true, + "linkSupport": true + }, + "selectionRange": { + "dynamicRegistration": true + }, + "callHierarchy": { + "dynamicRegistration": true + }, + "semanticTokens": { + "dynamicRegistration": true, + "tokenTypes": [ + "namespace", + "type", + "class", + "enum", + "interface", + "struct", + "typeParameter", + "parameter", + "variable", + "property", + "enumMember", + "event", + "function", + "method", + "macro", + "keyword", + "modifier", + "comment", + "string", + "number", + "regexp", + "operator" + ], + "tokenModifiers": [ + "declaration", + "definition", + "readonly", + "static", + "deprecated", + "abstract", + "async", + "modification", + "documentation", + "defaultLibrary" + ], + "formats": [ + "relative" + ], + "requests": { + "range": true, + "full": { + "delta": true + } + }, + "multilineTokenSupport": false, + "overlappingTokenSupport": false + }, + "linkedEditingRange": { + "dynamicRegistration": true + } + }, + "window": { + "showMessage": { + "messageActionItem": { + "additionalPropertiesSupport": true + } + }, + "showDocument": { + "support": true + }, + "workDoneProgress": true + }, + "general": { + "regularExpressions": { + "engine": "ECMAScript", + "version": "ES2020" + }, + "markdown": { + "parser": "marked", + "version": "1.1.0" + } + } + }, + "trace": "off", + "workspaceFolders": [ + { + "uri": "file://@ROOT@/", + "name": "sanity" + } + ] + } + }, + { + "jsonrpc": "2.0", + "method": "initialized", + "params": {} + }, + { + "jsonrpc": "2.0", + "method": "textDocument/didOpen", + "params": { + "textDocument": { + "uri": "file://@ROOT@/000hello/hello.vhdl", + "languageId": "vhdl", + "version": 1, + "text": "entity hello is\nend hello;\n\narchitecture behav of hello is\nbegin\n assert false report \"Hello VHDL world\" severity note; \u00e9\nend behav;\n" + } + } + }, + { + "jsonrpc": "2.0", + "method": "$/setTrace", + "params": { + "value": "off" + } + }, + { + "jsonrpc": "2.0", + "id": 1, + "method": "textDocument/documentSymbol", + "params": { + "textDocument": { + "uri": "file://@ROOT@/000hello/hello.vhdl" + } + } + }, + { + "jsonrpc": "2.0", + "id": 2, + "method": "shutdown" + } +] diff --git a/testsuite/pyunit/lsp/009ls122/replies.json b/testsuite/pyunit/lsp/009ls122/replies.json new file mode 100644 index 000000000..66c1cda26 --- /dev/null +++ b/testsuite/pyunit/lsp/009ls122/replies.json @@ -0,0 +1,158 @@ +[ + { + "jsonrpc": "2.0", + "id": 0, + "result": { + "capabilities": { + "textDocumentSync": { + "openClose": true, + "change": 2, + "save": { + "includeText": true + } + }, + "hoverProvider": false, + "definitionProvider": true, + "referencesProvider": false, + "documentHighlightProvider": false, + "documentSymbolProvider": true, + "codeActionProvider": false, + "documentFormattingProvider": false, + "documentRangeFormattingProvider": true, + "renameProvider": false + } + } + }, + { + "jsonrpc": "2.0", + "method": "textDocument/publishDiagnostics", + "params": { + "uri": "file://@ROOT@/000hello/hello.vhdl", + "diagnostics": [ + { + "source": "ghdl", + "range": { + "start": { + "line": 6, + "character": 0 + }, + "end": { + "line": 6, + "character": 0 + } + }, + "message": "'<=' is expected instead of 'end'", + "severity": 1 + }, + { + "source": "ghdl", + "range": { + "start": { + "line": 6, + "character": 0 + }, + "end": { + "line": 6, + "character": 0 + } + }, + "message": "primary expression expected", + "severity": 1 + }, + { + "source": "ghdl", + "range": { + "start": { + "line": 5, + "character": 57 + }, + "end": { + "line": 5, + "character": 57 + } + }, + "message": "';' expected at end of signal assignment", + "severity": 1, + "relatedInformation": [ + { + "location": { + "uri": "file://@ROOT@/000hello/hello.vhdl", + "range": { + "start": { + "line": 5, + "character": 57 + }, + "end": { + "line": 5, + "character": 57 + } + } + }, + "message": "(found: 'end')" + } + ] + }, + { + "source": "ghdl", + "range": { + "start": { + "line": 5, + "character": 56 + }, + "end": { + "line": 5, + "character": 56 + } + }, + "message": "no declaration for \"\u00e9\"", + "severity": 1 + } + ] + } + }, + { + "jsonrpc": "2.0", + "id": 1, + "result": [ + { + "kind": 2, + "name": "hello", + "location": { + "uri": "file://@ROOT@/000hello/hello.vhdl", + "range": { + "start": { + "line": 0, + "character": 0 + }, + "end": { + "line": 1, + "character": 0 + } + } + } + }, + { + "kind": 2, + "name": "behav", + "location": { + "uri": "file://@ROOT@/000hello/hello.vhdl", + "range": { + "start": { + "line": 3, + "character": 0 + }, + "end": { + "line": 6, + "character": 0 + } + } + } + } + ] + }, + { + "jsonrpc": "2.0", + "id": 2, + "result": null + } +] diff --git a/testsuite/pyunit/lsp/010ls28/adder.vhdl b/testsuite/pyunit/lsp/010ls28/adder.vhdl new file mode 100644 index 000000000..2b4e6d887 --- /dev/null +++ b/testsuite/pyunit/lsp/010ls28/adder.vhdl @@ -0,0 +1,20 @@ + library ieee; + use ieee.std_logic_1164.all; + + entity adder is + port( + a : in std_logic; + b : in std_logic; + o : out std_logic; + c : out std_logic + ); + end entity; + + architecture comb of adder is + + begin + + o <= a xor b; + c <= a and b; + + end; diff --git a/testsuite/pyunit/lsp/010ls28/cmds.json b/testsuite/pyunit/lsp/010ls28/cmds.json new file mode 100644 index 000000000..24ed0543b --- /dev/null +++ b/testsuite/pyunit/lsp/010ls28/cmds.json @@ -0,0 +1,470 @@ +[ + { + "jsonrpc": "2.0", + "id": 0, + "method": "initialize", + "params": { + "processId": 6311, + "clientInfo": { + "name": "Visual Studio Code", + "version": "1.68.1" + }, + "locale": "en-us", + "rootPath": "@ROOT@/010ls28", + "rootUri": "file://@ROOT@/010ls28", + "capabilities": { + "workspace": { + "applyEdit": true, + "workspaceEdit": { + "documentChanges": true, + "resourceOperations": [ + "create", + "rename", + "delete" + ], + "failureHandling": "textOnlyTransactional", + "normalizesLineEndings": true, + "changeAnnotationSupport": { + "groupsOnLabel": true + } + }, + "didChangeConfiguration": { + "dynamicRegistration": true + }, + "didChangeWatchedFiles": { + "dynamicRegistration": true + }, + "symbol": { + "dynamicRegistration": true, + "symbolKind": { + "valueSet": [ + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26 + ] + }, + "tagSupport": { + "valueSet": [ + 1 + ] + } + }, + "codeLens": { + "refreshSupport": true + }, + "executeCommand": { + "dynamicRegistration": true + }, + "configuration": true, + "workspaceFolders": true, + "semanticTokens": { + "refreshSupport": true + }, + "fileOperations": { + "dynamicRegistration": true, + "didCreate": true, + "didRename": true, + "didDelete": true, + "willCreate": true, + "willRename": true, + "willDelete": true + } + }, + "textDocument": { + "publishDiagnostics": { + "relatedInformation": true, + "versionSupport": false, + "tagSupport": { + "valueSet": [ + 1, + 2 + ] + }, + "codeDescriptionSupport": true, + "dataSupport": true + }, + "synchronization": { + "dynamicRegistration": true, + "willSave": true, + "willSaveWaitUntil": true, + "didSave": true + }, + "completion": { + "dynamicRegistration": true, + "contextSupport": true, + "completionItem": { + "snippetSupport": true, + "commitCharactersSupport": true, + "documentationFormat": [ + "markdown", + "plaintext" + ], + "deprecatedSupport": true, + "preselectSupport": true, + "tagSupport": { + "valueSet": [ + 1 + ] + }, + "insertReplaceSupport": true, + "resolveSupport": { + "properties": [ + "documentation", + "detail", + "additionalTextEdits" + ] + }, + "insertTextModeSupport": { + "valueSet": [ + 1, + 2 + ] + } + }, + "completionItemKind": { + "valueSet": [ + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25 + ] + } + }, + "hover": { + "dynamicRegistration": true, + "contentFormat": [ + "markdown", + "plaintext" + ] + }, + "signatureHelp": { + "dynamicRegistration": true, + "signatureInformation": { + "documentationFormat": [ + "markdown", + "plaintext" + ], + "parameterInformation": { + "labelOffsetSupport": true + }, + "activeParameterSupport": true + }, + "contextSupport": true + }, + "definition": { + "dynamicRegistration": true, + "linkSupport": true + }, + "references": { + "dynamicRegistration": true + }, + "documentHighlight": { + "dynamicRegistration": true + }, + "documentSymbol": { + "dynamicRegistration": true, + "symbolKind": { + "valueSet": [ + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26 + ] + }, + "hierarchicalDocumentSymbolSupport": true, + "tagSupport": { + "valueSet": [ + 1 + ] + }, + "labelSupport": true + }, + "codeAction": { + "dynamicRegistration": true, + "isPreferredSupport": true, + "disabledSupport": true, + "dataSupport": true, + "resolveSupport": { + "properties": [ + "edit" + ] + }, + "codeActionLiteralSupport": { + "codeActionKind": { + "valueSet": [ + "", + "quickfix", + "refactor", + "refactor.extract", + "refactor.inline", + "refactor.rewrite", + "source", + "source.organizeImports" + ] + } + }, + "honorsChangeAnnotations": false + }, + "codeLens": { + "dynamicRegistration": true + }, + "formatting": { + "dynamicRegistration": true + }, + "rangeFormatting": { + "dynamicRegistration": true + }, + "onTypeFormatting": { + "dynamicRegistration": true + }, + "rename": { + "dynamicRegistration": true, + "prepareSupport": true, + "prepareSupportDefaultBehavior": 1, + "honorsChangeAnnotations": true + }, + "documentLink": { + "dynamicRegistration": true, + "tooltipSupport": true + }, + "typeDefinition": { + "dynamicRegistration": true, + "linkSupport": true + }, + "implementation": { + "dynamicRegistration": true, + "linkSupport": true + }, + "colorProvider": { + "dynamicRegistration": true + }, + "foldingRange": { + "dynamicRegistration": true, + "rangeLimit": 5000, + "lineFoldingOnly": true + }, + "declaration": { + "dynamicRegistration": true, + "linkSupport": true + }, + "selectionRange": { + "dynamicRegistration": true + }, + "callHierarchy": { + "dynamicRegistration": true + }, + "semanticTokens": { + "dynamicRegistration": true, + "tokenTypes": [ + "namespace", + "type", + "class", + "enum", + "interface", + "struct", + "typeParameter", + "parameter", + "variable", + "property", + "enumMember", + "event", + "function", + "method", + "macro", + "keyword", + "modifier", + "comment", + "string", + "number", + "regexp", + "operator" + ], + "tokenModifiers": [ + "declaration", + "definition", + "readonly", + "static", + "deprecated", + "abstract", + "async", + "modification", + "documentation", + "defaultLibrary" + ], + "formats": [ + "relative" + ], + "requests": { + "range": true, + "full": { + "delta": true + } + }, + "multilineTokenSupport": false, + "overlappingTokenSupport": false + }, + "linkedEditingRange": { + "dynamicRegistration": true + } + }, + "window": { + "showMessage": { + "messageActionItem": { + "additionalPropertiesSupport": true + } + }, + "showDocument": { + "support": true + }, + "workDoneProgress": true + }, + "general": { + "regularExpressions": { + "engine": "ECMAScript", + "version": "ES2020" + }, + "markdown": { + "parser": "marked", + "version": "1.1.0" + } + } + }, + "trace": "off", + "workspaceFolders": [ + { + "uri": "file://@ROOT@/010ls28", + "name": "010ls28" + } + ] + } + }, + { + "jsonrpc": "2.0", + "method": "initialized", + "params": {} + }, + { + "jsonrpc": "2.0", + "method": "textDocument/didOpen", + "params": { + "textDocument": { + "uri": "file://@ROOT@/top.vhdl", + "languageId": "vhdl", + "version": 1, + "text": "library ieee;\nuse ieee.std_logic_1164.all;\n\nentity top is\n port (\n clk : in std_logic;\n sum : out std_logic\n );\nend entity;\n\narchitecture rtl of top is\nbegin\n\n adder : entity work.adder(comb)\n port map(\n a => clk,\n b => '1',\n o => sum,\n c => open\n );\n\nend architecture;\n" + } + } + }, + { + "jsonrpc": "2.0", + "id": 1, + "method": "textDocument/documentSymbol", + "params": { + "textDocument": { + "uri": "file://@ROOT@/top.vhdl" + } + } + }, + { + "jsonrpc": "2.0", + "method": "textDocument/didChange", + "params": { + "textDocument": { + "uri": "file://@ROOT@/top.vhdl", + "version": 2 + }, + "contentChanges": [ + { + "range": { + "start": { + "line": 18, + "character": 13 + }, + "end": { + "line": 18, + "character": 13 + } + }, + "rangeLength": 0, + "text": " " + } + ] + } + }, + { + "jsonrpc": "2.0", + "id": 2, + "method": "textDocument/documentSymbol", + "params": { + "textDocument": { + "uri": "file://@ROOT@/top.vhdl" + } + } + } +] diff --git a/testsuite/pyunit/lsp/010ls28/hdl-prj.json b/testsuite/pyunit/lsp/010ls28/hdl-prj.json new file mode 100644 index 000000000..51d4f6cf5 --- /dev/null +++ b/testsuite/pyunit/lsp/010ls28/hdl-prj.json @@ -0,0 +1,6 @@ +{ + "files" : [ + { "file" : "adder.vhdl", "language" : "vhdl" }, + { "file" : "top.vhdl", "language" : "vhdl" } + ] + } diff --git a/testsuite/pyunit/lsp/010ls28/replies.json b/testsuite/pyunit/lsp/010ls28/replies.json new file mode 100644 index 000000000..f67600637 --- /dev/null +++ b/testsuite/pyunit/lsp/010ls28/replies.json @@ -0,0 +1,190 @@ +[ + { + "jsonrpc": "2.0", + "id": 0, + "result": { + "capabilities": { + "textDocumentSync": { + "openClose": true, + "change": 2, + "save": { + "includeText": true + } + }, + "hoverProvider": false, + "definitionProvider": true, + "referencesProvider": false, + "documentHighlightProvider": false, + "documentSymbolProvider": true, + "codeActionProvider": false, + "documentFormattingProvider": false, + "documentRangeFormattingProvider": true, + "renameProvider": false + } + } + }, + { + "jsonrpc": "2.0", + "method": "textDocument/publishDiagnostics", + "params": { + "uri": "file://@ROOT@/top.vhdl", + "diagnostics": [] + } + }, + { + "jsonrpc": "2.0", + "id": 1, + "result": [ + { + "kind": 2, + "name": "top", + "location": { + "uri": "file://@ROOT@/top.vhdl", + "range": { + "start": { + "line": 3, + "character": 0 + }, + "end": { + "line": 8, + "character": 0 + } + } + } + }, + { + "kind": 2, + "name": "rtl", + "location": { + "uri": "file://@ROOT@/top.vhdl", + "range": { + "start": { + "line": 10, + "character": 0 + }, + "end": { + "line": 21, + "character": 0 + } + } + } + }, + { + "kind": 6, + "name": "adder", + "location": { + "uri": "file://@ROOT@/top.vhdl", + "range": { + "start": { + "line": 13, + "character": 2 + }, + "end": { + "line": 13, + "character": 7 + } + } + }, + "containerName": { + "kind": 2, + "name": "rtl", + "location": { + "uri": "file://@ROOT@/top.vhdl", + "range": { + "start": { + "line": 10, + "character": 0 + }, + "end": { + "line": 21, + "character": 0 + } + } + } + } + } + ] + }, + { + "jsonrpc": "2.0", + "method": "textDocument/publishDiagnostics", + "params": { + "uri": "file://@ROOT@/top.vhdl", + "diagnostics": [] + } + }, + { + "jsonrpc": "2.0", + "id": 2, + "result": [ + { + "kind": 2, + "name": "top", + "location": { + "uri": "file://@ROOT@/top.vhdl", + "range": { + "start": { + "line": 3, + "character": 0 + }, + "end": { + "line": 8, + "character": 0 + } + } + } + }, + { + "kind": 2, + "name": "rtl", + "location": { + "uri": "file://@ROOT@/top.vhdl", + "range": { + "start": { + "line": 10, + "character": 0 + }, + "end": { + "line": 21, + "character": 0 + } + } + } + }, + { + "kind": 6, + "name": "adder", + "location": { + "uri": "file://@ROOT@/top.vhdl", + "range": { + "start": { + "line": 13, + "character": 2 + }, + "end": { + "line": 13, + "character": 7 + } + } + }, + "containerName": { + "kind": 2, + "name": "rtl", + "location": { + "uri": "file://@ROOT@/top.vhdl", + "range": { + "start": { + "line": 10, + "character": 0 + }, + "end": { + "line": 21, + "character": 0 + } + } + } + } + } + ] + } +] diff --git a/testsuite/pyunit/lsp/010ls28/top.vhdl b/testsuite/pyunit/lsp/010ls28/top.vhdl new file mode 100644 index 000000000..d371cce2e --- /dev/null +++ b/testsuite/pyunit/lsp/010ls28/top.vhdl @@ -0,0 +1,22 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity top is + port ( + clk : in std_logic; + sum : out std_logic + ); +end entity; + +architecture rtl of top is +begin + + adder : entity work.adder(comb) + port map( + a => clk, + b => '1', + o => sum, + c => open + ); + +end architecture; diff --git a/testsuite/pyunit/lsp/011closediag/adder.vhdl b/testsuite/pyunit/lsp/011closediag/adder.vhdl new file mode 100644 index 000000000..7d5b62c97 --- /dev/null +++ b/testsuite/pyunit/lsp/011closediag/adder.vhdl @@ -0,0 +1,20 @@ + library ieee; + use ieee.std_logic_1164.all; + + entity adder is + port( + a : in std_logic; + b : in std_logic; + o : out std_logic; + c : out std_logic + ); + end entity; + + architecture comb of adder is + signal nouse : boolean; + begin + + o <= a xor b; + c <= a and b; + + end; diff --git a/testsuite/pyunit/lsp/011closediag/cmds.json b/testsuite/pyunit/lsp/011closediag/cmds.json new file mode 100644 index 000000000..95980b7ee --- /dev/null +++ b/testsuite/pyunit/lsp/011closediag/cmds.json @@ -0,0 +1,443 @@ +[ + { + "jsonrpc": "2.0", + "id": 0, + "method": "initialize", + "params": { + "processId": 10037, + "clientInfo": { + "name": "Visual Studio Code", + "version": "1.68.1" + }, + "locale": "en-us", + "rootPath": "@ROOT@/011closediag", + "rootUri": "file://@ROOT@/011closediag", + "capabilities": { + "workspace": { + "applyEdit": true, + "workspaceEdit": { + "documentChanges": true, + "resourceOperations": [ + "create", + "rename", + "delete" + ], + "failureHandling": "textOnlyTransactional", + "normalizesLineEndings": true, + "changeAnnotationSupport": { + "groupsOnLabel": true + } + }, + "didChangeConfiguration": { + "dynamicRegistration": true + }, + "didChangeWatchedFiles": { + "dynamicRegistration": true + }, + "symbol": { + "dynamicRegistration": true, + "symbolKind": { + "valueSet": [ + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26 + ] + }, + "tagSupport": { + "valueSet": [ + 1 + ] + } + }, + "codeLens": { + "refreshSupport": true + }, + "executeCommand": { + "dynamicRegistration": true + }, + "configuration": true, + "workspaceFolders": true, + "semanticTokens": { + "refreshSupport": true + }, + "fileOperations": { + "dynamicRegistration": true, + "didCreate": true, + "didRename": true, + "didDelete": true, + "willCreate": true, + "willRename": true, + "willDelete": true + } + }, + "textDocument": { + "publishDiagnostics": { + "relatedInformation": true, + "versionSupport": false, + "tagSupport": { + "valueSet": [ + 1, + 2 + ] + }, + "codeDescriptionSupport": true, + "dataSupport": true + }, + "synchronization": { + "dynamicRegistration": true, + "willSave": true, + "willSaveWaitUntil": true, + "didSave": true + }, + "completion": { + "dynamicRegistration": true, + "contextSupport": true, + "completionItem": { + "snippetSupport": true, + "commitCharactersSupport": true, + "documentationFormat": [ + "markdown", + "plaintext" + ], + "deprecatedSupport": true, + "preselectSupport": true, + "tagSupport": { + "valueSet": [ + 1 + ] + }, + "insertReplaceSupport": true, + "resolveSupport": { + "properties": [ + "documentation", + "detail", + "additionalTextEdits" + ] + }, + "insertTextModeSupport": { + "valueSet": [ + 1, + 2 + ] + } + }, + "completionItemKind": { + "valueSet": [ + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25 + ] + } + }, + "hover": { + "dynamicRegistration": true, + "contentFormat": [ + "markdown", + "plaintext" + ] + }, + "signatureHelp": { + "dynamicRegistration": true, + "signatureInformation": { + "documentationFormat": [ + "markdown", + "plaintext" + ], + "parameterInformation": { + "labelOffsetSupport": true + }, + "activeParameterSupport": true + }, + "contextSupport": true + }, + "definition": { + "dynamicRegistration": true, + "linkSupport": true + }, + "references": { + "dynamicRegistration": true + }, + "documentHighlight": { + "dynamicRegistration": true + }, + "documentSymbol": { + "dynamicRegistration": true, + "symbolKind": { + "valueSet": [ + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26 + ] + }, + "hierarchicalDocumentSymbolSupport": true, + "tagSupport": { + "valueSet": [ + 1 + ] + }, + "labelSupport": true + }, + "codeAction": { + "dynamicRegistration": true, + "isPreferredSupport": true, + "disabledSupport": true, + "dataSupport": true, + "resolveSupport": { + "properties": [ + "edit" + ] + }, + "codeActionLiteralSupport": { + "codeActionKind": { + "valueSet": [ + "", + "quickfix", + "refactor", + "refactor.extract", + "refactor.inline", + "refactor.rewrite", + "source", + "source.organizeImports" + ] + } + }, + "honorsChangeAnnotations": false + }, + "codeLens": { + "dynamicRegistration": true + }, + "formatting": { + "dynamicRegistration": true + }, + "rangeFormatting": { + "dynamicRegistration": true + }, + "onTypeFormatting": { + "dynamicRegistration": true + }, + "rename": { + "dynamicRegistration": true, + "prepareSupport": true, + "prepareSupportDefaultBehavior": 1, + "honorsChangeAnnotations": true + }, + "documentLink": { + "dynamicRegistration": true, + "tooltipSupport": true + }, + "typeDefinition": { + "dynamicRegistration": true, + "linkSupport": true + }, + "implementation": { + "dynamicRegistration": true, + "linkSupport": true + }, + "colorProvider": { + "dynamicRegistration": true + }, + "foldingRange": { + "dynamicRegistration": true, + "rangeLimit": 5000, + "lineFoldingOnly": true + }, + "declaration": { + "dynamicRegistration": true, + "linkSupport": true + }, + "selectionRange": { + "dynamicRegistration": true + }, + "callHierarchy": { + "dynamicRegistration": true + }, + "semanticTokens": { + "dynamicRegistration": true, + "tokenTypes": [ + "namespace", + "type", + "class", + "enum", + "interface", + "struct", + "typeParameter", + "parameter", + "variable", + "property", + "enumMember", + "event", + "function", + "method", + "macro", + "keyword", + "modifier", + "comment", + "string", + "number", + "regexp", + "operator" + ], + "tokenModifiers": [ + "declaration", + "definition", + "readonly", + "static", + "deprecated", + "abstract", + "async", + "modification", + "documentation", + "defaultLibrary" + ], + "formats": [ + "relative" + ], + "requests": { + "range": true, + "full": { + "delta": true + } + }, + "multilineTokenSupport": false, + "overlappingTokenSupport": false + }, + "linkedEditingRange": { + "dynamicRegistration": true + } + }, + "window": { + "showMessage": { + "messageActionItem": { + "additionalPropertiesSupport": true + } + }, + "showDocument": { + "support": true + }, + "workDoneProgress": true + }, + "general": { + "regularExpressions": { + "engine": "ECMAScript", + "version": "ES2020" + }, + "markdown": { + "parser": "marked", + "version": "1.1.0" + } + } + }, + "trace": "off", + "workspaceFolders": [ + { + "uri": "file://@ROOT@/011closediag", + "name": "011closediag" + } + ] + } + }, + { + "jsonrpc": "2.0", + "method": "initialized", + "params": {} + }, + { + "jsonrpc": "2.0", + "method": "textDocument/didOpen", + "params": { + "textDocument": { + "uri": "file://@ROOT@/011closediag/adder.vhdl", + "languageId": "vhdl", + "version": 1, + "text": " library ieee;\n use ieee.std_logic_1164.all;\n \n entity adder is\n port(\n a : in std_logic;\n b : in std_logic;\n o : out std_logic;\n c : out std_logic\n );\n end entity;\n \n architecture comb of adder is\n signal nouse : boolean;\n begin\n \n o <= a xor b;\n c <= a and b;\n \n end;\n" + } + } + }, + { + "jsonrpc": "2.0", + "id": 1, + "method": "textDocument/documentSymbol", + "params": { + "textDocument": { + "uri": "file://@ROOT@/011closediag/adder.vhdl" + } + } + }, + { + "jsonrpc": "2.0", + "method": "textDocument/didClose", + "params": { + "textDocument": { + "uri": "file://@ROOT@/011closediag/adder.vhdl" + } + } + } +] diff --git a/testsuite/pyunit/lsp/011closediag/replies.json b/testsuite/pyunit/lsp/011closediag/replies.json new file mode 100644 index 000000000..4f119fad5 --- /dev/null +++ b/testsuite/pyunit/lsp/011closediag/replies.json @@ -0,0 +1,98 @@ +[ + { + "jsonrpc": "2.0", + "id": 0, + "result": { + "capabilities": { + "textDocumentSync": { + "openClose": true, + "change": 2, + "save": { + "includeText": true + } + }, + "hoverProvider": false, + "definitionProvider": true, + "referencesProvider": false, + "documentHighlightProvider": false, + "documentSymbolProvider": true, + "codeActionProvider": false, + "documentFormattingProvider": false, + "documentRangeFormattingProvider": true, + "renameProvider": false + } + } + }, + { + "jsonrpc": "2.0", + "method": "textDocument/publishDiagnostics", + "params": { + "uri": "file://@ROOT@/011closediag/adder.vhdl", + "diagnostics": [ + { + "source": "ghdl", + "range": { + "start": { + "line": 13, + "character": 11 + }, + "end": { + "line": 13, + "character": 11 + } + }, + "message": "signal \"nouse\" is never referenced", + "severity": 2 + } + ] + } + }, + { + "jsonrpc": "2.0", + "id": 1, + "result": [ + { + "kind": 2, + "name": "adder", + "location": { + "uri": "file://@ROOT@/011closediag/adder.vhdl", + "range": { + "start": { + "line": 3, + "character": 2 + }, + "end": { + "line": 10, + "character": 2 + } + } + } + }, + { + "kind": 2, + "name": "comb", + "location": { + "uri": "file://@ROOT@/011closediag/adder.vhdl", + "range": { + "start": { + "line": 12, + "character": 2 + }, + "end": { + "line": 19, + "character": 1 + } + } + } + } + ] + }, + { + "jsonrpc": "2.0", + "method": "textDocument/publishDiagnostics", + "params": { + "uri": "file://@ROOT@/011closediag/adder.vhdl", + "diagnostics": [] + } + } +] diff --git a/testsuite/pyunit/lsp/LanguageServer.py b/testsuite/pyunit/lsp/LanguageServer.py index ad55439e1..79c891868 100644 --- a/testsuite/pyunit/lsp/LanguageServer.py +++ b/testsuite/pyunit/lsp/LanguageServer.py @@ -223,3 +223,21 @@ class Test008_Error_NoFile(JSONTest): def test_Request_Response(self): self._RequestResponse("cmds.json", "replies.json") + +class Test009_ls_122(JSONTest): + subdir = Path("009ls122") + + def test_Request_Response(self): + self._RequestResponse("cmds.json", "replies.json") + +class Test010_ls_28(JSONTest): + subdir = Path("010ls28") + + def test_Request_Response(self): + self._RequestResponse("cmds.json", "replies.json") + +class Test011_closediag(JSONTest): + subdir = Path("011closediag") + + def test_Request_Response(self): + self._RequestResponse("cmds.json", "replies.json") diff --git a/testsuite/pyunit/lsp/README b/testsuite/pyunit/lsp/README new file mode 100644 index 000000000..ec8f614e2 --- /dev/null +++ b/testsuite/pyunit/lsp/README @@ -0,0 +1,45 @@ +# To run the LSP testsuite +Assuming pyGHDL is installed (Hint: use pip install -U -e), + +> pytest + +or + +> pytest-3 + + +# To add a test + +Enable traces: + +> export GHDL_LS_TRACE=ghdl-ls + +Run the session + +> code . +(or your preferred editor) + +This creates two files (or more): `ghdl-ls.in` and `ghdl-ls.out` +Those are raw dumps of the LSP data. + +Create a new test directory (increment the number): + +> mkdir 099mytest +> cd 099mytest + +Transforms those files in json (which are easier to read and to process): + +> python3 -m pyGHDL.lsp.lsptools lsp2json < xxx/ghdl-ls.in > cmds.json +> python3 -m pyGHDL.lsp.lsptools lsp2json < xxx/ghdl-ls.out > replies.json + +Substitute the root directory with `@ROOT@` (for privacy and relocation): +(The root directory is the parent directory of the test, so it is + xxx/ghdl/testsuite/pyunit/lsp) + +> sed -i -e 's!/home/me/test!@ROOT@' cmds.json +> sed -i -e 's!/home/me/test!@ROOT@' replies.json + +Add a test in LanguageServer.py (use existing tests as a template) + +Adjust or improve this file. + diff --git a/testsuite/synth/arr01/tb_arr04.vhdl b/testsuite/synth/arr01/tb_arr04.vhdl index 51801b258..63e01fa85 100644 --- a/testsuite/synth/arr01/tb_arr04.vhdl +++ b/testsuite/synth/arr01/tb_arr04.vhdl @@ -21,6 +21,8 @@ begin constant sov : std_logic_vector := b"0101"; constant v_v : std_logic_vector := b"0011"; constant r_v : std_logic_vector := b"0001"; + -- reg0 0001 + -- reg1 0011 begin clk <= '0'; rst <= '1'; diff --git a/testsuite/synth/issue2054/flip_flop.vhdl b/testsuite/synth/issue2054/flip_flop.vhdl new file mode 100644 index 000000000..a5bbe5d27 --- /dev/null +++ b/testsuite/synth/issue2054/flip_flop.vhdl @@ -0,0 +1,16 @@ +library ieee; +use ieee.numeric_std.all; +use ieee.std_logic_1164.all; + +entity flip_flop is + port ( + clk : in std_logic; + wire : in std_logic; + reg : out std_logic + ); +end; + +architecture a_flip_flop of flip_flop is +begin + reg <= wire when rising_edge(clk); +end; diff --git a/testsuite/synth/issue2054/testcase2.vhdl b/testsuite/synth/issue2054/testcase2.vhdl new file mode 100644 index 000000000..614c4f29a --- /dev/null +++ b/testsuite/synth/issue2054/testcase2.vhdl @@ -0,0 +1,22 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity testcase is + port ( + clk : in std_logic; + i : in std_ulogic_vector(63 downto 0); + o : out std_ulogic_vector(63 downto 0) + ); +end entity testcase; + +architecture behaviour of testcase is + signal edge : std_ulogic_vector(63 downto 0); +begin + testcase_0: process(clk) + begin + if rising_edge(clk) then + edge <= i; + o <= edge; + end if; + end process; +end behaviour; diff --git a/testsuite/synth/issue2054/testcase3.vhdl b/testsuite/synth/issue2054/testcase3.vhdl new file mode 100644 index 000000000..8323db17e --- /dev/null +++ b/testsuite/synth/issue2054/testcase3.vhdl @@ -0,0 +1,22 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity testcase is + port ( + clk : in std_logic; + i : in std_ulogic_vector(63 downto 0); + o : out std_ulogic_vector(63 downto 0) + ); +end entity testcase; + +architecture behaviour of testcase is + signal edge : std_ulogic_vector(63 downto 0) := (others => '1'); +begin + testcase_0: process(clk) + begin + if rising_edge(clk) then + edge <= i; + o <= edge; + end if; + end process; +end behaviour; diff --git a/testsuite/synth/issue2054/testsuite.sh b/testsuite/synth/issue2054/testsuite.sh new file mode 100755 index 000000000..a51e970f4 --- /dev/null +++ b/testsuite/synth/issue2054/testsuite.sh @@ -0,0 +1,20 @@ +#! /bin/sh + +. ../../testenv.sh + +synth --out=verilog flip_flop.vhdl -e > syn_flip_flop.v +if grep "input wire" syn_flip_flop.v; then + exit 1 +fi + +synth --out=verilog testcase2.vhdl -e > syn_testcase2.v +if grep "assign edge" syn_testcase2.v; then + exit 1 +fi + +synth --out=verilog testcase3.vhdl -e > syn_testcase3.v +if grep "edge =" syn_testcase3.v; then + exit 1 +fi + +echo "Test successful" diff --git a/testsuite/synth/issue2062/fxt.vhdl b/testsuite/synth/issue2062/fxt.vhdl new file mode 100644 index 000000000..8ee26e5a2 --- /dev/null +++ b/testsuite/synth/issue2062/fxt.vhdl @@ -0,0 +1,15 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.fixed_pkg.all; + +entity fxt is port ( + a : in std_logic_vector(6 downto 0); + y : out ufixed(3 downto -2)); +end entity; + +architecture beh of fxt is +begin + y <= to_ufixed(a, 5, 1); +end beh; diff --git a/testsuite/synth/issue2062/fxt2.vhdl b/testsuite/synth/issue2062/fxt2.vhdl new file mode 100644 index 000000000..a63ff4d7e --- /dev/null +++ b/testsuite/synth/issue2062/fxt2.vhdl @@ -0,0 +1,14 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.fixed_pkg.all; + +entity fxt2 is port ( + a : in std_logic_vector(5 downto 0); + y : out ufixed(3 downto -2)); +end entity; + +architecture beh of fxt2 is +begin + y <= to_ufixed(a, 6, 1); +end beh; diff --git a/testsuite/synth/issue2062/repro.vhdl b/testsuite/synth/issue2062/repro.vhdl new file mode 100644 index 000000000..2b676415c --- /dev/null +++ b/testsuite/synth/issue2062/repro.vhdl @@ -0,0 +1,12 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity repro is port ( + a : in std_logic_vector(5 downto 0); + y : out std_ulogic_vector(3 downto -2)); +end entity; + +architecture beh of repro is +begin + y <= to_stdulogicvector(a); +end beh; diff --git a/testsuite/synth/issue2062/testsuite.sh b/testsuite/synth/issue2062/testsuite.sh new file mode 100755 index 000000000..7ca626bd5 --- /dev/null +++ b/testsuite/synth/issue2062/testsuite.sh @@ -0,0 +1,10 @@ +#! /bin/sh + +. ../../testenv.sh + +synth_only repro + +GHDL_STD_FLAGS=--std=08 +synth_only fxt2 + +echo "Test successful" diff --git a/testsuite/synth/issue2063/array_index_crash.vhdl b/testsuite/synth/issue2063/array_index_crash.vhdl new file mode 100644 index 000000000..2be4b0206 --- /dev/null +++ b/testsuite/synth/issue2063/array_index_crash.vhdl @@ -0,0 +1,32 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity array_index_crash is +end entity; + +architecture behaviour of array_index_crash is + + constant SIZE : integer := 8; + constant AMIN : integer := 0; + constant AMAX : integer := 7; + + subtype data_t is std_logic_vector((SIZE-1) downto 0); + type data_arr_t is array(AMIN to AMAX) of data_t; + + function initialise return data_arr_t is + variable ret : data_arr_t; + variable itv : integer; + begin + for i in AMIN to AMAX + loop + itv := 2*AMAX; + -- vvv oops + ret(itv) := std_logic_vector(to_unsigned(itv, SIZE)); + end loop; + return ret; + end function; + + constant data_arr : data_arr_t := initialise; +begin +end architecture; diff --git a/testsuite/synth/issue2063/testsuite.sh b/testsuite/synth/issue2063/testsuite.sh new file mode 100755 index 000000000..d9e33478f --- /dev/null +++ b/testsuite/synth/issue2063/testsuite.sh @@ -0,0 +1,7 @@ +#! /bin/sh + +. ../../testenv.sh + +synth_failure array_index_crash.vhdl -e + +echo "Test successful" diff --git a/testsuite/synth/issue2072/swaptest.vhdl b/testsuite/synth/issue2072/swaptest.vhdl new file mode 100644 index 000000000..11ea76368 --- /dev/null +++ b/testsuite/synth/issue2072/swaptest.vhdl @@ -0,0 +1,34 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity swaptest is +port ( + clk : in std_logic; + d : in unsigned(7 downto 0); + q : out unsigned(7 downto 0) +); +end entity; + +architecture rtl of swaptest is + +FUNCTION bswap(v : unsigned) RETURN unsigned IS + VARIABLE u: unsigned(0 TO v'length-1) :=v; + VARIABLE x: unsigned(0 TO v'length-1); +BEGIN + FOR i IN 0 TO v'length-1 LOOP + x((v'length-1)-i):=u(i); + END LOOP; + return x; +END FUNCTION; + +begin + + process(clk) begin + if rising_edge(clk) then + q(7 downto 1) <= bswap(d(7 downto 1)); + end if; + end process; + +end architecture; + diff --git a/testsuite/synth/issue2072/tb_swaptest.vhdl b/testsuite/synth/issue2072/tb_swaptest.vhdl new file mode 100644 index 000000000..194f3c9d0 --- /dev/null +++ b/testsuite/synth/issue2072/tb_swaptest.vhdl @@ -0,0 +1,37 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library std; +use std.textio.all; + +entity tb_swaptest is +end tb_swaptest; + +architecture behaviour of tb_swaptest +is + constant clk_period : time := 10 ns; + signal clk : std_logic; + signal d : unsigned(7 downto 0) := X"c5"; + signal q : unsigned(7 downto 0); +begin + + clk_process: process + begin + for i in 1 to 10 loop + clk <= '0'; + wait for clk_period/2; + clk <= '1'; + wait for clk_period/2; + end loop; + wait; + end process; + + st : entity work.swaptest + port map ( + clk => clk, + d => d, + q => q + ); + +end architecture; diff --git a/testsuite/synth/issue2072/testsuite.sh b/testsuite/synth/issue2072/testsuite.sh new file mode 100755 index 000000000..755f1f4ec --- /dev/null +++ b/testsuite/synth/issue2072/testsuite.sh @@ -0,0 +1,9 @@ +#! /bin/sh + +. ../../testenv.sh + +for t in swaptest; do + synth_tb $t +done + +echo "Test successful" diff --git a/testsuite/synth/issue2073/ivoice.vhdl b/testsuite/synth/issue2073/ivoice.vhdl new file mode 100644 index 000000000..4fd2ee6b6 --- /dev/null +++ b/testsuite/synth/issue2073/ivoice.vhdl @@ -0,0 +1,105 @@ +-- Massively reduced testcase - the actual file I'm attempting to build is here: +-- https://github.com/MiSTer-devel/Intv_MiSTer/blob/master/rtl/intv/ivoice.vhd + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY ivoice IS + PORT ( + sound : OUT signed(15 downto 0); + clksys : IN std_logic; --- 43MHz ... 48MHz + reset_na : IN std_logic + ); +END ENTITY ivoice; + +ARCHITECTURE rtl OF ivoice IS + SUBTYPE sv16 IS signed(15 DOWNTO 0); + SUBTYPE uv8 IS unsigned(7 DOWNTO 0); + SUBTYPE uv16 IS unsigned(15 DOWNTO 0); + SUBTYPE uv19 IS unsigned(18 DOWNTO 0); + SUBTYPE uv20 IS unsigned(19 DOWNTO 0); + SUBTYPE int16 IS integer RANGE -32768 TO 32767; + SUBTYPE uint4 IS natural RANGE 0 TO 15; + SUBTYPE uint5 IS natural RANGE 0 TO 31; + SUBTYPE uint16 IS natural RANGE 0 TO 65535; + + TYPE enum_state IS ( + sIDLE,sDECODE1,sDECODE2,sDECODE3,sMICROCODE, + sGENE1,sGENE2,sGENE3,sGENE4, + sCALC01,sCALC02,sCALC11,sCALC12,sCALC21,sCALC22, + sCALC31,sCALC32,sCALC41,sCALC42,sCALC51,sCALC52, + sSOUND); + SIGNAL state,state2 : enum_state; + + FUNCTION bswap(v : unsigned) RETURN unsigned IS + VARIABLE u,x: unsigned(0 TO v'length-1) :=v; + BEGIN + FOR i IN 0 TO v'length-1 LOOP + x(v'length-1-i):=u(i); + END LOOP; + return x; + END FUNCTION; + + SIGNAL pc,ret_pc : uv19; + + FUNCTION sat(i : integer) RETURN integer IS + BEGIN + IF i>127 THEN RETURN 127; END IF; + IF i<-128 THEN RETURN -128; END IF; + RETURN i; + END FUNCTION; + + SIGNAL samp : int16 := 0; + + SIGNAL fifoptr : uint5; + SIGNAL romd : uv16; + SIGNAL fifod : uv20; + SIGNAL rom_a : uint16; + SIGNAL rom_dr : uv8; + +BEGIN + + ------------------------------------------------------------------------------ + -- Sequencer + Machine:PROCESS(clksys,reset_na) IS + VARIABLE romd_v,fifod_v,imm_v,inst_v,code_v : uv8; + VARIABLE tmp_v : uv16; + VARIABLE len_v : uint4; + VARIABLE pc_v : uv19; + VARIABLE branch_v : boolean; + BEGIN + IF rising_edge(clksys) THEN + ------------------------------------------------------ + + romd_v:=romd(7+to_integer(pc(2 DOWNTO 0)) DOWNTO + to_integer(pc(2 DOWNTO 0))); + + code_v:=romd_v; + + CASE state IS + + ------------------------------------------------- + WHEN sDECODE1 => + inst_v:=bswap(code_v); + state<=sDECODE2; + IF inst_v(7 DOWNTO 4)="0000" THEN + state<=sGENE1; -- If Zero repeat, skip instruction + END IF; + + ----------------------------------------------- + -- Sound output. + WHEN sSOUND => + sound<=to_signed(sat(samp/4)*256,16); + + when others => + null; + + ----------------------------------------------- + END CASE; + + --------------------------------------------------- + END IF; + END PROCESS; + +END ARCHITECTURE rtl; diff --git a/testsuite/synth/issue2073/ivoice2.vhdl b/testsuite/synth/issue2073/ivoice2.vhdl new file mode 100644 index 000000000..995c245fe --- /dev/null +++ b/testsuite/synth/issue2073/ivoice2.vhdl @@ -0,0 +1,18 @@ +-- Massively reduced testcase - the actual file I'm attempting to build is: +-- https://github.com/MiSTer-devel/Intv_MiSTer/blob/master/rtl/intv/ivoice.vhd + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +ENTITY ivoice2 IS + PORT ( + pc : natural range 0 to 7; + romd : std_logic_vector(15 DOWNTO 0); + sound : OUT std_logic_vector(7 downto 0) + ); +END ; + +ARCHITECTURE rtl OF ivoice2 IS +BEGIN + sound <=romd(7+pc downto pc); +END ARCHITECTURE rtl; diff --git a/testsuite/synth/issue2073/tb_ivoice2.vhdl b/testsuite/synth/issue2073/tb_ivoice2.vhdl new file mode 100644 index 000000000..133a3ca2a --- /dev/null +++ b/testsuite/synth/issue2073/tb_ivoice2.vhdl @@ -0,0 +1,51 @@ +entity tb_ivoice2 is +end tb_ivoice2; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_ivoice2 is + signal romd : std_logic_vector (15 downto 0) := b"1010_0100_0100_0011"; + signal pc : natural range 0 to 7; + signal res : std_logic_vector (7 downto 0); +begin + dut: entity work.ivoice2 + port map (pc, romd, res); + + process + begin + pc <= 0; + wait for 1 ns; + assert res = b"0100_0011" severity failure; + + pc <= 1; + wait for 1 ns; + assert res = b"0_0100_001" severity failure; + + pc <= 2; + wait for 1 ns; + assert res = b"00_0100_00" severity failure; + + pc <= 3; + wait for 1 ns; + assert res = b"100_0100_0" severity failure; + + pc <= 4; + wait for 1 ns; + assert res = b"0100_0100" severity failure; + + pc <= 5; + wait for 1 ns; + assert res = b"0_0100_010" severity failure; + + pc <= 6; + wait for 1 ns; + assert res = b"10_0100_01" severity failure; + + pc <= 7; + wait for 1 ns; + assert res = b"010_0100_0" severity failure; + + wait; + end process; +end behav; diff --git a/testsuite/synth/issue2073/testsuite.sh b/testsuite/synth/issue2073/testsuite.sh new file mode 100755 index 000000000..73683bc8c --- /dev/null +++ b/testsuite/synth/issue2073/testsuite.sh @@ -0,0 +1,11 @@ +#! /bin/sh + +. ../../testenv.sh + +synth_only ivoice + +synth_tb ivoice2 + +clean + +echo "Test successful" diff --git a/testsuite/synth/issue2074/bitvec.vhdl b/testsuite/synth/issue2074/bitvec.vhdl new file mode 100644 index 000000000..abd0786e3 --- /dev/null +++ b/testsuite/synth/issue2074/bitvec.vhdl @@ -0,0 +1,16 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity bitvec is +port ( + clk : in std_logic; + d : in bit_vector(7 downto 0); + q : out bit_vector(7 downto 0) +); +end entity; + +architecture rtl of bitvec is + constant a : bit_vector(7 downto 0) := X"5a"; +begin + q <= d and a; +end architecture; diff --git a/testsuite/synth/issue2074/testsuite.sh b/testsuite/synth/issue2074/testsuite.sh new file mode 100755 index 000000000..27ce42d50 --- /dev/null +++ b/testsuite/synth/issue2074/testsuite.sh @@ -0,0 +1,9 @@ +#! /bin/sh + +. ../../testenv.sh + +synth_only bitvec + +clean + +echo "Test successful" diff --git a/testsuite/synth/issue2080/ent.vhdl b/testsuite/synth/issue2080/ent.vhdl new file mode 100644 index 000000000..d667ddfe0 --- /dev/null +++ b/testsuite/synth/issue2080/ent.vhdl @@ -0,0 +1,35 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity identity is + port ( + x: in std_logic_vector(7 downto 0); + y: out std_logic_vector(7 downto 0) + ); +end entity; + +architecture a of identity is +begin + y <= x; +end architecture; + +--- + +library ieee; +use ieee.std_logic_1164.all; + +entity ent is + port ( + a: in std_logic_vector(7 downto 0); + b: out std_logic_vector(7 downto 0) + ); +end entity; + +architecture a of ent is + function transform(val: std_logic_vector) return std_logic_vector is + begin + return (7 downto 0 => '0'); + end function; +begin + identity: entity work.identity port map (x => transform(a), y => b); +end architecture; diff --git a/testsuite/synth/issue2080/tb_ent.vhdl b/testsuite/synth/issue2080/tb_ent.vhdl new file mode 100644 index 000000000..d9aed6d71 --- /dev/null +++ b/testsuite/synth/issue2080/tb_ent.vhdl @@ -0,0 +1,20 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity tb_ent is +end entity; + +architecture a of tb_ent is + signal a, b : std_logic_vector(7 downto 0); +begin + uut: entity work.ent port map (a => a, b => b); + + process + begin + a <= x"42"; + wait for 1 ns; + assert b = x"00"; + + wait; + end process; +end architecture; diff --git a/testsuite/synth/issue2080/testsuite.sh b/testsuite/synth/issue2080/testsuite.sh new file mode 100755 index 000000000..5c1da263d --- /dev/null +++ b/testsuite/synth/issue2080/testsuite.sh @@ -0,0 +1,7 @@ +#! /bin/sh + +. ../../testenv.sh + +synth_tb ent + +echo "Test successful" diff --git a/testsuite/synth/issue2081/ent.vhdl b/testsuite/synth/issue2081/ent.vhdl new file mode 100644 index 000000000..f9fefd528 --- /dev/null +++ b/testsuite/synth/issue2081/ent.vhdl @@ -0,0 +1,16 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity ent is +end entity; + +architecture a of ent is + signal foo : std_logic_vector(7 downto 0); +begin + process(foo) + begin + if foo /= x"00" then + assert false; + end if; + end process; +end architecture; diff --git a/testsuite/synth/issue2081/testsuite.sh b/testsuite/synth/issue2081/testsuite.sh new file mode 100755 index 000000000..363692cc2 --- /dev/null +++ b/testsuite/synth/issue2081/testsuite.sh @@ -0,0 +1,9 @@ +#! /bin/sh + +. ../../testenv.sh + +synth ent.vhdl -e > syn_ent.vhdl + +synth_failure -Werror=nowrite ent.vhdl -e + +echo "Test successful" diff --git a/testsuite/synth/issue2083/bug.vhdl b/testsuite/synth/issue2083/bug.vhdl new file mode 100644 index 000000000..fd8695ce1 --- /dev/null +++ b/testsuite/synth/issue2083/bug.vhdl @@ -0,0 +1,31 @@ +library IEEE; +use IEEE.std_logic_1164.all; + +entity bug is + port ( + clk : in std_ulogic + ); +end bug; + +architecture behav of bug is + type fields_t is record + field_a : std_ulogic_vector; + field_b : std_ulogic; + end record; + + type field_array_t is array(natural range<>) of fields_t; + + function fun return std_ulogic is + variable field_array : field_array_t(0 to 1)(field_a(0 to 31)); + begin + if field_array(0).field_b = '1' then -- this causes the crash + --nothing + end if; + return '0'; + end function; + + constant data : std_ulogic := fun; +begin + +end architecture; + diff --git a/testsuite/synth/issue2083/testsuite.sh b/testsuite/synth/issue2083/testsuite.sh new file mode 100755 index 000000000..c355095b7 --- /dev/null +++ b/testsuite/synth/issue2083/testsuite.sh @@ -0,0 +1,8 @@ +#! /bin/sh + +. ../../testenv.sh + +GHDL_STD_FLAGS=--std=08 +synth_only bug + +echo "Test successful" diff --git a/testsuite/synth/issue2084/bug.vhdl b/testsuite/synth/issue2084/bug.vhdl new file mode 100644 index 000000000..847ac0f1b --- /dev/null +++ b/testsuite/synth/issue2084/bug.vhdl @@ -0,0 +1,15 @@ +library IEEE; +use IEEE.std_logic_1164.all; + +entity bug is + port ( + src : in std_ulogic_vector(31 downto 0) + ); +end bug; + +architecture rtl of bug is + type array_t is array(0 to 0) of src'subtype; + signal s : array_t; +begin + +end architecture; diff --git a/testsuite/synth/issue2084/testsuite.sh b/testsuite/synth/issue2084/testsuite.sh new file mode 100755 index 000000000..c355095b7 --- /dev/null +++ b/testsuite/synth/issue2084/testsuite.sh @@ -0,0 +1,8 @@ +#! /bin/sh + +. ../../testenv.sh + +GHDL_STD_FLAGS=--std=08 +synth_only bug + +echo "Test successful" diff --git a/testsuite/synth/issue2085/bug.vhdl b/testsuite/synth/issue2085/bug.vhdl new file mode 100644 index 000000000..0b719a075 --- /dev/null +++ b/testsuite/synth/issue2085/bug.vhdl @@ -0,0 +1,27 @@ +library IEEE; +use IEEE.std_logic_1164.all; + +entity bug is + port ( + clk : in std_ulogic; + src : in std_ulogic_vector(15 downto 0); + dst : out std_ulogic_vector(16 downto 0) + ); +end bug; + +architecture rtl of bug is +begin + +process(clk) + function fun(val : std_ulogic_vector) return std_ulogic_vector is + variable tmp : val'subtype; --this causes the crash + begin + return val; + end function; +begin + if rising_edge(clk) then + dst <= '0' & fun(src); + end if; +end process; + +end architecture; diff --git a/testsuite/synth/issue2085/testsuite.sh b/testsuite/synth/issue2085/testsuite.sh new file mode 100755 index 000000000..c355095b7 --- /dev/null +++ b/testsuite/synth/issue2085/testsuite.sh @@ -0,0 +1,8 @@ +#! /bin/sh + +. ../../testenv.sh + +GHDL_STD_FLAGS=--std=08 +synth_only bug + +echo "Test successful" diff --git a/testsuite/synth/issue2086/repro4.vhdl b/testsuite/synth/issue2086/repro4.vhdl new file mode 100644 index 000000000..ef4da6a42 --- /dev/null +++ b/testsuite/synth/issue2086/repro4.vhdl @@ -0,0 +1,28 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity repro4 is + port ( + rst : std_logic; + clk : std_logic; + de : std_logic; + vs_o : out std_logic); +end; + +architecture synth of repro4 is + type mem_t is array(0 to 15) of std_logic; + + signal mem : mem_t; + signal addr : integer range mem_t'range; +begin + process(rst, clk) + begin + if rst = '1' then + addr <= 0; + elsif rising_edge(clk) then + vs_o <= mem(addr); + mem(addr) <= de; + addr <= addr+1; + end if; + end process; +end; diff --git a/testsuite/synth/issue2086/testsuite.sh b/testsuite/synth/issue2086/testsuite.sh new file mode 100755 index 000000000..258102547 --- /dev/null +++ b/testsuite/synth/issue2086/testsuite.sh @@ -0,0 +1,7 @@ +#! /bin/sh + +. ../../testenv.sh + +synth_only repro4 + +echo "Test successful" diff --git a/testsuite/synth/issue2088/bug.vhdl b/testsuite/synth/issue2088/bug.vhdl new file mode 100644 index 000000000..c71baf120 --- /dev/null +++ b/testsuite/synth/issue2088/bug.vhdl @@ -0,0 +1,35 @@ +library IEEE; +use IEEE.std_logic_1164.all; + +entity bug is +port( + clk : in std_ulogic +); +end entity; + +architecture rtl of bug is + + type table_t is array (natural range<>, natural range<>) of integer; + + function fun1(table : table_t) return integer is + constant len : natural := table'length(2); + begin + return len; + end function; + + function fun2(table : table_t) return integer is + variable tmp : natural; + begin + tmp := 0; + for i in table'range(2) loop + tmp := tmp+1; + end loop; + return tmp; + end function; + + constant table : table_t(0 to 15, 0 to 31) := (others => (others => 0)); + constant l1 : natural := fun1(table); + constant l2 : natural := fun2(table); +begin + +end architecture; diff --git a/testsuite/synth/issue2088/bug2.vhdl b/testsuite/synth/issue2088/bug2.vhdl new file mode 100644 index 000000000..029811162 --- /dev/null +++ b/testsuite/synth/issue2088/bug2.vhdl @@ -0,0 +1,37 @@ +library IEEE; +use IEEE.std_logic_1164.all; + +entity bug2 is +port( + clk : in std_ulogic +); +end entity; + +architecture rtl of bug2 is + + type table_t is array (natural range<>, natural range<>) of integer; + + function fun1(table : table_t) return integer is + constant len : natural := table'length(2); + begin + return len; + end function; + + function fun2(table : table_t) return integer is + variable tmp : natural; + begin + tmp := 0; + for i in table'range(2) loop + tmp := tmp+1; + end loop; + return tmp; + end function; + + constant table : table_t(0 to 15, 0 to 31) := (others => (others => 0)); + constant l1 : natural := fun1(table); + constant l2 : natural := fun2(table); +begin + + assert table'left(1) = 0; + assert table'right(2) = 31; +end architecture; diff --git a/testsuite/synth/issue2088/bug3.vhdl b/testsuite/synth/issue2088/bug3.vhdl new file mode 100644 index 000000000..cca04c866 --- /dev/null +++ b/testsuite/synth/issue2088/bug3.vhdl @@ -0,0 +1,36 @@ +library IEEE; +use IEEE.std_logic_1164.all; + +entity bug2 is +port( + clk : in std_ulogic +); +end entity; + +architecture rtl of bug2 is + + type table_t is array (natural range<>, natural range<>) of integer; + + function fun1(table : table_t) return integer is + constant len : natural := table'length(2); + begin + return len; + end function; + + function fun2(table : table_t) return integer is + variable tmp : natural; + begin + tmp := 0; + for i in table'range(2) loop + tmp := tmp+1; + end loop; + return tmp; + end function; + + constant table : table_t(0 to 15, 0 to 31) := (others => (others => 0)); + constant l1 : natural := fun1(table); + constant l2 : natural := fun2(table); +begin + + assert table'right(2) = 15; -- Wrong +end architecture; diff --git a/testsuite/synth/issue2088/testsuite.sh b/testsuite/synth/issue2088/testsuite.sh new file mode 100755 index 000000000..76b9779b7 --- /dev/null +++ b/testsuite/synth/issue2088/testsuite.sh @@ -0,0 +1,9 @@ +#! /bin/sh + +. ../../testenv.sh + +synth_only bug +synth_only bug2 +synth_failure bug3.vhdl -e + +echo "Test successful" diff --git a/testsuite/synth/issue2089/bug.vhdl b/testsuite/synth/issue2089/bug.vhdl new file mode 100644 index 000000000..b36b08786 --- /dev/null +++ b/testsuite/synth/issue2089/bug.vhdl @@ -0,0 +1,42 @@ +library IEEE; +use IEEE.std_logic_1164.all; + +entity bug is +port( + clk : in std_ulogic +); +end entity; + +library IEEE; +use IEEE.std_logic_1164.all; + +entity ent is +port( + data : in std_ulogic_vector +); +end entity; + +architecture rtl of bug is + + type data_t is record + a : std_ulogic; + b : std_ulogic; + end record; + + function to_sulv(data : data_t) return std_ulogic_vector is + constant ret : std_ulogic_vector(1 downto 0) := data.a & data.b; + begin + return ret; + end function; + + constant data : data_t := (a => '0', b => '1'); +begin + u0 : entity work.ent + port map(data => to_sulv(data)); +end architecture; + +architecture rtl of ent is + +begin + +end architecture; diff --git a/testsuite/synth/issue2089/testsuite.sh b/testsuite/synth/issue2089/testsuite.sh new file mode 100755 index 000000000..6ec49749f --- /dev/null +++ b/testsuite/synth/issue2089/testsuite.sh @@ -0,0 +1,7 @@ +#! /bin/sh + +. ../../testenv.sh + +synth_only bug + +echo "Test successful" diff --git a/testsuite/synth/issue2090/bug.vhdl b/testsuite/synth/issue2090/bug.vhdl new file mode 100644 index 000000000..bdf4f4207 --- /dev/null +++ b/testsuite/synth/issue2090/bug.vhdl @@ -0,0 +1,63 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity bug is +port( + clk : in std_ulogic +); +end entity; + +library IEEE; +use IEEE.std_logic_1164.all; + +entity ent is +generic( + LEN : natural +); +port( + data : in std_ulogic_vector(LEN-1 downto 0) +); +end entity; + +architecture rtl of bug is + + constant ROWS : natural := 5; + constant COLS : natural := 5; + constant DATA_WIDTH : natural := 1; + + type data_t is record + value : unsigned(DATA_WIDTH*8-1 downto 0); + end record data_t; + + type table_t is array (0 to COLS-1, 0 to ROWS-1) of data_t; + signal table : table_t; + + function table_to_sulv(table : table_t) return std_ulogic_vector is + variable ret : std_ulogic_vector(COLS*ROWS*DATA_WIDTH*8-1 downto 0); + variable idx : natural := 1; + begin + for y in 0 to ROWS-1 loop + for x in 0 to COLS-1 loop + ret(idx*8-1 downto (idx-1)*8) := std_ulogic_vector(table(x,y).value); + idx := idx+1; + end loop; + end loop; + return ret; + end function; + +begin + u0 : entity work.ent + generic map( + LEN => COLS*ROWS*DATA_WIDTH*8 + ) + port map( + data => table_to_sulv(table) + ); +end architecture; + +architecture rtl of ent is + +begin + +end architecture; diff --git a/testsuite/synth/issue2090/testsuite.sh b/testsuite/synth/issue2090/testsuite.sh new file mode 100755 index 000000000..6ec49749f --- /dev/null +++ b/testsuite/synth/issue2090/testsuite.sh @@ -0,0 +1,7 @@ +#! /bin/sh + +. ../../testenv.sh + +synth_only bug + +echo "Test successful" diff --git a/testsuite/synth/issue2092/testcase.vhdl b/testsuite/synth/issue2092/testcase.vhdl new file mode 100644 index 000000000..a2659bad2 --- /dev/null +++ b/testsuite/synth/issue2092/testcase.vhdl @@ -0,0 +1,25 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity testcase is + port( + rst : in std_ulogic; + clk : in std_ulogic + ); +end entity testcase; + +architecture rtl of testcase is + + component testcase2 port ( + rst : in std_ulogic; + clk : in std_ulogic + ); + end component; + +begin + testcase2_0: testcase2 + port map ( + clk => clk, + rst => rst + ); +end architecture rtl; diff --git a/testsuite/synth/issue2092/testsuite.sh b/testsuite/synth/issue2092/testsuite.sh new file mode 100755 index 000000000..1d1fb9466 --- /dev/null +++ b/testsuite/synth/issue2092/testsuite.sh @@ -0,0 +1,11 @@ +#! /bin/sh + +. ../../testenv.sh + +synth --out=verilog testcase.vhdl -e > syn_testcase.v + +if grep "module testcase2" syn_testcase.v; then + exit 1 +fi + +echo "Test successful" diff --git a/testsuite/synth/issue2099/bug.vhdl b/testsuite/synth/issue2099/bug.vhdl new file mode 100644 index 000000000..0117c10da --- /dev/null +++ b/testsuite/synth/issue2099/bug.vhdl @@ -0,0 +1,32 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity bug is +port( + clk : in std_ulogic +); +end entity; + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity ent is +port( + data : in unsigned(15 downto 0) +); +end entity; + +architecture rtl of bug is + + signal tmp : std_ulogic_vector(31 downto 0); + +begin + u0 : entity work.ent + port map(data => unsigned(tmp(15 downto 0))); +end architecture; + +architecture rtl of ent is +begin +end architecture; diff --git a/testsuite/synth/issue2099/testsuite.sh b/testsuite/synth/issue2099/testsuite.sh new file mode 100755 index 000000000..6ec49749f --- /dev/null +++ b/testsuite/synth/issue2099/testsuite.sh @@ -0,0 +1,7 @@ +#! /bin/sh + +. ../../testenv.sh + +synth_only bug + +echo "Test successful" diff --git a/testsuite/synth/issue2109/bug.vhdl b/testsuite/synth/issue2109/bug.vhdl new file mode 100644 index 000000000..c514c6f99 --- /dev/null +++ b/testsuite/synth/issue2109/bug.vhdl @@ -0,0 +1,17 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity bug is +generic( + tmp : std_ulogic_vector(0 downto 1) := "" +); +port( + val : out std_ulogic_vector(0 downto 1) +); +end entity; + +architecture rtl of bug is +begin + val <= tmp; +end architecture; diff --git a/testsuite/synth/issue2109/testsuite.sh b/testsuite/synth/issue2109/testsuite.sh new file mode 100755 index 000000000..1361b7a0a --- /dev/null +++ b/testsuite/synth/issue2109/testsuite.sh @@ -0,0 +1,11 @@ +#! /bin/sh + +. ../../testenv.sh + +synth --out=verilog bug.vhdl -e > syn_bug.v + +if grep val syn_bug.v; then + exit 1 +fi + +echo "Test successful" diff --git a/testsuite/synth/issue2113/a.vhdl b/testsuite/synth/issue2113/a.vhdl new file mode 100644 index 000000000..82f8039cd --- /dev/null +++ b/testsuite/synth/issue2113/a.vhdl @@ -0,0 +1,59 @@ +library IEEE; +use IEEE.std_logic_1164.all; + +entity a is + port( + irq : out std_ulogic + ); +end a; + +library IEEE; +use IEEE.std_logic_1164.all; + +entity b is + generic( + NUM_CHANNELS : positive := 4 + ); + port( + src_channel : in integer range 0 to NUM_CHANNELS-1; + src_valid : in std_ulogic; + src_ready : out std_ulogic + ); +end b; + +architecture struct of a is + + signal src_valid : std_ulogic; + signal src_ready : std_ulogic; +begin + u0 : entity work.b + generic map( + NUM_CHANNELS => 1 + ) + port map( + src_channel => 0, + src_valid => src_valid, + src_ready => src_ready + ); +end architecture; + +architecture behav of b is +begin + process(all) + variable ready : std_ulogic; + variable channel_ready : std_ulogic; + begin + ready := '1'; + for i in 0 to NUM_CHANNELS-1 loop + if i = src_channel and src_valid = '1' then + channel_ready := '0'; + else + channel_ready := '1'; + end if; + ready := ready and channel_ready; + end loop; + + src_ready <= ready; + end process; + +end architecture; diff --git a/testsuite/synth/issue2113/testsuite.sh b/testsuite/synth/issue2113/testsuite.sh new file mode 100755 index 000000000..9ab046cc4 --- /dev/null +++ b/testsuite/synth/issue2113/testsuite.sh @@ -0,0 +1,15 @@ +#! /bin/sh + +. ../../testenv.sh + +GHDL_STD_FLAGS=--std=08 +synth --out=verilog -Wno-nowrite a.vhdl -e > syn_a.v + +if grep channel syn_a.v; then + exit 1 +fi +if grep "0'" syn_a.v; then + exit 1; +fi + +echo "Test successful" diff --git a/testsuite/synth/issue2119/test.vhdl b/testsuite/synth/issue2119/test.vhdl new file mode 100644 index 000000000..755ea5ed8 --- /dev/null +++ b/testsuite/synth/issue2119/test.vhdl @@ -0,0 +1,58 @@ +-- Title : Testcase for unbounded records +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +package test_pkg is + type test_rec is record + vec_bound : std_logic_vector(7 downto 0); + vec_unbound : std_logic_vector; + single_bit : std_logic; + end record test_rec; +end test_pkg; + +------------------------------------------------------------------------------------------------------------------------------------------------------ +-- Inner module +------------------------------------------------------------------------------------------------------------------------------------------------------ +library ieee; +use ieee.std_logic_1164.all; + +use work.test_pkg.all; + +entity test_impl is + + port ( + clk : in std_logic; + rec_out : out test_rec + ); + +end entity test_impl; +architecture str of test_impl is +begin -- architecture str +end architecture str; + +------------------------------------------------------------------------------------------------------------------------------------------------------ +-- Outer Wrapper +------------------------------------------------------------------------------------------------------------------------------------------------------ +library ieee; +use ieee.std_logic_1164.all; +use work.test_pkg.all; +entity test is + + generic ( + unbound_len : natural := 10 + ); + port ( + clk : in std_logic; + rec_out : out test_rec(vec_unbound(unbound_len-1 downto 0))); +end entity test; + +architecture str of test is + +begin -- architecture str + test_impl_1: entity work.test_impl + port map ( + clk => clk, -- [in std_logic] + rec_out => rec_out); -- [out test_rec] +end architecture str; diff --git a/testsuite/synth/issue2119/testsuite.sh b/testsuite/synth/issue2119/testsuite.sh new file mode 100755 index 000000000..75ca5f68d --- /dev/null +++ b/testsuite/synth/issue2119/testsuite.sh @@ -0,0 +1,9 @@ +#! /bin/sh + +. ../../testenv.sh + +GHDL_STD_FLAGS=--std=08 + +synth_only test + +echo "Test successful" |