testsuite/gna/issue2115/ent.vhdl


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

entity ent is
end entity;

architecture a of ent is
begin
  process
    variable b : boolean;
    variable l : std.textio.line;
  begin
    b := false;
    std.textio.write(l, b);
    report l.all & " should be false";
    l := null;
    b := true;
    std.textio.write(l, b);
    report l.all & " should be true";
    wait;
  end process;
end;