testsuite/synth/issue2113/testsuite.sh


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

#! /bin/sh

. ../../testenv.sh

GHDL_STD_FLAGS=--std=08
synth --out=verilog -Wno-nowrite a.vhdl -e > syn_a.v

if grep channel syn_a.v; then
  exit 1
fi
if grep "0'" syn_a.v; then
  exit 1;
fi

echo "Test successful"