testsuite/synth/issue2092/testcase.vhdl


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

library ieee;
use ieee.std_logic_1164.all;

entity testcase is
    port(
        rst : in std_ulogic;
        clk : in std_ulogic
    );
end entity testcase;

architecture rtl of testcase is

    component testcase2 port (
        rst : in std_ulogic;
        clk : in std_ulogic
    );
    end component;

begin
    testcase2_0: testcase2
        port map (
            clk => clk,
            rst => rst
        );
end architecture rtl;