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Merge pull request #1811 from PeterCrozier/typedef_scope
N. Engelhardt
2020-03-30
1
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+7
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Support module/package/interface/block scope for typedef names.
Peter Crozier
2020-03-23
1
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+7
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Add support for SystemVerilog-style `define to Verilog frontend
Rupert Swarbrick
2020-03-27
4
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+50
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Merge pull request #1806 from YosysHQ/mwk/techmap-replace-fix
Claire Wolf
2020-03-26
1
-0
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+18
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techmap: Fix cell names with _TECHMAP_REPLACE_.*
Marcin Kościelnicki
2020-03-23
1
-0
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+18
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Merge pull request #1763 from boqwxp/issue1762
N. Engelhardt
2020-03-23
5
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+19
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Do not warn on empty selection with prefixed `arg_memb`.
Alberto Gonzalez
2020-03-23
1
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+5
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Suppress warnings for empty `select` arguments when `-count` or `-assert-*` o...
Alberto Gonzalez
2020-03-23
1
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+2
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Add tests for `select` command warnings.
Alberto Gonzalez
2020-03-23
3
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+12
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Merge pull request #1803 from Grazfather/typedef
N. Engelhardt
2020-03-23
7
-25
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+26
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Revert typedef tests to standard grammar.
Peter
2020-03-22
7
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+26
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Add test for abc9+mince issue
David Shah
2020-03-20
1
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+17
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fsm_extract: Initialize celltypes with full design.
Marcin Kościelnicki
2020-03-19
1
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+33
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Merge pull request #1774 from boqwxp/exec
N. Engelhardt
2020-03-19
1
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+6
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Add test for `exec` command.
Alberto Gonzalez
2020-03-16
1
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+6
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fix argument order for macOS compatibility
N. Engelhardt
2020-03-18
1
-3
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+3
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Merge pull request #1759 from zeldin/constant_with_comment_redux
Miodrag Milanović
2020-03-14
2
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+24
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Add regression tests for new handling of comments in constants
Marcus Comstedt
2020-03-14
2
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+24
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Merge pull request #1754 from boqwxp/precise_locations
Miodrag Milanović
2020-03-14
1
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+8
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verilog: add test
Eddie Hung
2020-03-11
1
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+8
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Added back tests for logger
Miodrag Milanovic
2020-03-13
4
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+24
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Merge pull request #1721 from YosysHQ/dave/tribuf-unused
David Shah
2020-03-10
1
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+14
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deminout: Don't demote inouts with unused bits
David Shah
2020-03-04
1
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+14
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Fix partsel expr bit width handling and add test case
Claire Wolf
2020-03-08
1
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+4
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rpc test: make frontend listen before launching yosys & introduce safeguard i...
N. Engelhardt
2020-03-06
1
-1
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+2
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tests: extend tests/arch/run-tests.sh for defines
Eddie Hung
2020-03-05
1
-3
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+14
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Merge pull request #1718 from boqwxp/precise_locations
Claire Wolf
2020-03-03
2
-4
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+4
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Change attribute search value to specify precise location instead of simple l...
Alberto Gonzalez
2020-02-24
1
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+2
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Change attribute search value to specify precise location instead of simple l...
Alberto Gonzalez
2020-02-24
1
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+2
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Merge pull request #1519 from YosysHQ/eddie/submod_po
Claire Wolf
2020-03-03
1
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+124
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Merge branch 'master' into eddie/submod_po
Eddie Hung
2020-02-01
83
-175
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+2399
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Add a quick testcase for unknown modules as inout
Eddie Hung
2019-12-09
1
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+24
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iopadmap: Look harder for already-present buffers. (#1731)
Marcelina Kościelnicka
2020-03-02
1
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+21
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Merge pull request #1724 from YosysHQ/eddie/abc9_specify
Eddie Hung
2020-03-02
6
-7
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+10
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Revert "Fix tests/arch/xilinx/fsm.ys to count flops only"
Eddie Hung
2020-02-27
1
-3
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+9
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Cleanup tests
Eddie Hung
2020-02-27
2
-1
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+1
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Update bug1630.ys to use -lut 4 instead of lut file
Eddie Hung
2020-02-27
1
-1
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+1
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Fix tests/arch/xilinx/fsm.ys to count flops only
Eddie Hung
2020-02-27
1
-9
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+3
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Update simple_abc9 tests
Eddie Hung
2020-02-27
3
-5
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+8
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ast: fixes #1710; do not generate RTLIL for unreachable ternary
Eddie Hung
2020-02-27
1
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+30
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Merge pull request #1703 from YosysHQ/eddie/specify_improve
Eddie Hung
2020-02-21
2
-3
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+47
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clean: ignore specify-s inside cells when determining whether to keep
Eddie Hung
2020-02-19
1
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+20
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verilog: ignore ranges too without -specify
Eddie Hung
2020-02-13
1
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+7
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verilog: improve specify support when not in -specify mode
Eddie Hung
2020-02-13
2
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+1
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verilog: ignore '&&&' when not in -specify mode
Eddie Hung
2020-02-13
1
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+6
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specify: system timing checks to accept min:typ:max triple
Eddie Hung
2020-02-13
1
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+7
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verilog: fix $specify3 check
Eddie Hung
2020-02-13
1
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+7
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Merge pull request #1642 from jjj11x/jjj11x/sv-enum
Claire Wolf
2020-02-20
4
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+68
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add attributes for enumerated values in ilang
Jeff Wang
2020-02-17
2
-3
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+3
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scoped enum tests
Jeff Wang
2020-01-16
1
-1
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+13
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