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| author | Eddie Hung <eddie@fpgeh.com> | 2020-02-13 13:06:13 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-02-13 13:06:13 -0800 |
| commit | 2e51dc1856aae456e15cafd484997bfbd102175e (patch) | |
| tree | e446b57a8d99be177068c96e15e4f9753ec8b402 /tests | |
| parent | b523ecf2f45f80488412781ba9a3455a71d64d62 (diff) | |
| download | yosys-2e51dc1856aae456e15cafd484997bfbd102175e.tar.gz yosys-2e51dc1856aae456e15cafd484997bfbd102175e.tar.bz2 yosys-2e51dc1856aae456e15cafd484997bfbd102175e.zip | |
verilog: ignore '&&&' when not in -specify mode
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/various/specify.v | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/tests/various/specify.v b/tests/various/specify.v index 5006e4c38..aa8aca4bc 100644 --- a/tests/various/specify.v +++ b/tests/various/specify.v @@ -51,3 +51,9 @@ specify $setuphold(d, posedge clk, 1:2:3, 4:5:6); endspecify endmodule + +module test5(input clk, d, e, output q); +specify + $setup(d, posedge clk &&& e, 1:2:3); +endspecify +endmodule |