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| author | Eddie Hung <eddie@fpgeh.com> | 2020-02-13 12:13:12 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-02-27 10:17:29 -0800 |
| commit | 977262c8033b8778a32d4f29a77c64ea5a2799bd (patch) | |
| tree | 0c21d2c46e9cdcf81692afaa0648e49be0df23d1 /tests | |
| parent | e22fee6cdd905535c50c9b6d96a89e994944ea2c (diff) | |
| download | yosys-977262c8033b8778a32d4f29a77c64ea5a2799bd.tar.gz yosys-977262c8033b8778a32d4f29a77c64ea5a2799bd.tar.bz2 yosys-977262c8033b8778a32d4f29a77c64ea5a2799bd.zip | |
Update simple_abc9 tests
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/simple_abc9/abc.box | 2 | ||||
| -rw-r--r-- | tests/simple_abc9/abc9.v | 7 | ||||
| -rwxr-xr-x | tests/simple_abc9/run-test.sh | 4 |
3 files changed, 8 insertions, 5 deletions
diff --git a/tests/simple_abc9/abc.box b/tests/simple_abc9/abc.box deleted file mode 100644 index a8801d807..000000000 --- a/tests/simple_abc9/abc.box +++ /dev/null @@ -1,2 +0,0 @@ -MUXF8 1 0 3 1 -1 1 1 diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v index e5837d480..688b47586 100644 --- a/tests/simple_abc9/abc9.v +++ b/tests/simple_abc9/abc9.v @@ -213,8 +213,13 @@ module arbiter (clk, rst, request, acknowledge, grant, grant_valid, grant_encode input rst; endmodule -(* abc9_box_id=1, whitebox *) +(* abc9_box, blackbox *) module MUXF8(input I0, I1, S, output O); +specify + (I0 => O) = 0; + (I1 => O) = 0; + (S => O) = 0; +endspecify endmodule // Citation: https://github.com/alexforencich/verilog-ethernet diff --git a/tests/simple_abc9/run-test.sh b/tests/simple_abc9/run-test.sh index 32d7a80ca..424d8f417 100755 --- a/tests/simple_abc9/run-test.sh +++ b/tests/simple_abc9/run-test.sh @@ -25,8 +25,8 @@ exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v *.sv EXTRA_FLAGS="-n 300 -p synth -run coarse; \ opt -full; \ techmap; \ - abc9 -lut 4 -box ../abc.box; \ + abc9 -lut 4; \ clean; \ check -assert; \ select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_ %%; \ - setattr -mod -unset whitebox'" + setattr -mod -unset blackbox'" |