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| author | Eddie Hung <eddie@fpgeh.com> | 2020-02-27 16:55:55 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-02-27 16:55:55 -0800 |
| commit | 5bba9c3640971e25544f2053b31eb152c138c3af (patch) | |
| tree | ada4dabc8e3326edeecf9c133589085fb5bdbdc4 /tests | |
| parent | 825b96fdcffedec02b4eaaa5f9c4aee5bfc6942a (diff) | |
| download | yosys-5bba9c3640971e25544f2053b31eb152c138c3af.tar.gz yosys-5bba9c3640971e25544f2053b31eb152c138c3af.tar.bz2 yosys-5bba9c3640971e25544f2053b31eb152c138c3af.zip | |
ast: fixes #1710; do not generate RTLIL for unreachable ternary
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/various/bug1710.ys | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/tests/various/bug1710.ys b/tests/various/bug1710.ys new file mode 100644 index 000000000..c2ecf3c90 --- /dev/null +++ b/tests/various/bug1710.ys @@ -0,0 +1,30 @@ +logger -werror "out of bounds" +read_verilog <<EOT +module Example; + + parameter FLAG = 1; + wire [3:0] inp; + + reg out1; + initial out1 = FLAG ? &inp[2:0] : &inp[4:0]; + + reg out2; + initial + if (FLAG) + out2 = &inp[2:0]; + else + out2 = &inp[4:0]; + + wire out3; + assign out3 = FLAG ? &inp[2:0] : &inp[4:0]; + + wire out4; + generate + if (FLAG) + assign out4 = &inp[2:0]; + else + assign out4 = &inp[4:0]; + endgenerate + +endmodule +EOT |