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| author | Eddie Hung <eddie@fpgeh.com> | 2020-02-13 17:58:43 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-02-13 17:58:43 -0800 |
| commit | d20c1dac73e344dda73ec2b526ffb764efc9fdd8 (patch) | |
| tree | 77397933b425f31f0684572daa2df01cc39fd182 /tests | |
| parent | 6b58c1820c7bbacb4730af40e10592823b0eb15c (diff) | |
| download | yosys-d20c1dac73e344dda73ec2b526ffb764efc9fdd8.tar.gz yosys-d20c1dac73e344dda73ec2b526ffb764efc9fdd8.tar.bz2 yosys-d20c1dac73e344dda73ec2b526ffb764efc9fdd8.zip | |
verilog: ignore ranges too without -specify
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/various/specify.v | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/tests/various/specify.v b/tests/various/specify.v index 5655ded21..c160d2ec4 100644 --- a/tests/various/specify.v +++ b/tests/various/specify.v @@ -55,3 +55,10 @@ specify $setup(d, posedge clk &&& e, 1:2:3); endspecify endmodule + +module test6(input clk, d, e, output q); +specify + (d[0] *> q[0]) = (3,1); + (posedge clk[0] => (q[0] +: d[0])) = (3,1); +endspecify +endmodule |