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author | Claire Wolf <clifford@clifford.at> | 2020-02-20 18:17:25 +0100 |
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committer | GitHub <noreply@github.com> | 2020-02-20 18:17:25 +0100 |
commit | cd044a2bb6adf7a5e00d4a6c075e9489d852d733 (patch) | |
tree | 025e868ba44465bba10799be98e89e1aea77894a /tests | |
parent | cd60f079d6c96e1d8a00c3c081fab1148d432b44 (diff) | |
parent | 1c16311d104caa19e8aff35a0df1595c73fa1638 (diff) | |
download | yosys-cd044a2bb6adf7a5e00d4a6c075e9489d852d733.tar.gz yosys-cd044a2bb6adf7a5e00d4a6c075e9489d852d733.tar.bz2 yosys-cd044a2bb6adf7a5e00d4a6c075e9489d852d733.zip |
Merge pull request #1642 from jjj11x/jjj11x/sv-enum
Enum support
Diffstat (limited to 'tests')
-rw-r--r-- | tests/svtypes/enum_simple.sv | 47 | ||||
-rw-r--r-- | tests/svtypes/enum_simple.ys | 5 | ||||
-rw-r--r-- | tests/svtypes/typedef_package.sv | 3 | ||||
-rw-r--r-- | tests/svtypes/typedef_scopes.sv | 14 |
4 files changed, 68 insertions, 1 deletions
diff --git a/tests/svtypes/enum_simple.sv b/tests/svtypes/enum_simple.sv new file mode 100644 index 000000000..ccaf50da0 --- /dev/null +++ b/tests/svtypes/enum_simple.sv @@ -0,0 +1,47 @@ + +module enum_simple(input clk, input rst); + + enum {s0, s1, s2, s3} test_enum; + typedef enum logic [1:0] { + ts0, ts1, ts2, ts3 + } states_t; + (states_t) state; + (states_t) enum_const = ts1; + + always @(posedge clk) begin + if (rst) begin + test_enum <= s3; + state <= ts0; + end else begin + //test_enum + if (test_enum == s0) + test_enum <= s1; + else if (test_enum == s1) + test_enum <= s2; + else if (test_enum == s2) + test_enum <= s3; + else if (test_enum == s3) + test_enum <= s0; + else + assert(1'b0); //should be unreachable + + //state + if (state == ts0) + state <= ts1; + else if (state == ts1) + state <= ts2; + else if (state == ts2) + state <= ts0; + else + assert(1'b0); //should be unreachable + end + end + + always @(*) begin + assert(state != 2'h3); + assert(s0 == '0); + assert(ts0 == '0); + assert(enum_const == ts1); + end + +endmodule diff --git a/tests/svtypes/enum_simple.ys b/tests/svtypes/enum_simple.ys new file mode 100644 index 000000000..79981657b --- /dev/null +++ b/tests/svtypes/enum_simple.ys @@ -0,0 +1,5 @@ + +read_verilog -sv enum_simple.sv +hierarchy; proc; opt +sat -verify -seq 1 -set-at 1 rst 1 -tempinduct -prove-asserts -show-all + diff --git a/tests/svtypes/typedef_package.sv b/tests/svtypes/typedef_package.sv index a1e16d4b1..b766f10cf 100644 --- a/tests/svtypes/typedef_package.sv +++ b/tests/svtypes/typedef_package.sv @@ -1,11 +1,14 @@ package pkg; typedef logic [7:0] uint8_t; + typedef enum logic [7:0] {bb=8'hBB} enum8_t; endpackage module top; (* keep *) (pkg::uint8_t) a = 8'hAA; + (* keep *) (pkg::enum8_t) b_enum = pkg::bb; always @* assert(a == 8'hAA); + always @* assert(b_enum == 8'hBB); endmodule diff --git a/tests/svtypes/typedef_scopes.sv b/tests/svtypes/typedef_scopes.sv index faa385bd6..1c45c7057 100644 --- a/tests/svtypes/typedef_scopes.sv +++ b/tests/svtypes/typedef_scopes.sv @@ -1,23 +1,35 @@ typedef logic [3:0] outer_uint4_t; +typedef enum logic {s0, s1} outer_enum_t; module top; (outer_uint4_t) u4_i = 8'hA5; + (outer_enum_t) enum4_i = s0; always @(*) assert(u4_i == 4'h5); + always @(*) assert(enum4_i == 1'b0); typedef logic [3:0] inner_type; + typedef enum logic [2:0] {s2=2, s3, s4} inner_enum_t; (inner_type) inner_i1 = 8'h5A; + (inner_enum_t) inner_enum1 = s3; always @(*) assert(inner_i1 == 4'hA); + always @(*) assert(inner_enum1 == 3'h3); if (1) begin: genblock typedef logic [7:0] inner_type; - (inner_type) inner_gb_i = 8'hA5; + parameter (inner_type) inner_const = 8'hA5; + typedef enum logic [2:0] {s5=5, s6, s7} inner_enum_t; + (inner_type) inner_gb_i = inner_const; //8'hA5; + (inner_enum_t) inner_gb_enum1 = s7; always @(*) assert(inner_gb_i == 8'hA5); + always @(*) assert(inner_gb_enum1 == 3'h7); end (inner_type) inner_i2 = 8'h42; + (inner_enum_t) inner_enum2 = s4; always @(*) assert(inner_i2 == 4'h2); + always @(*) assert(inner_enum2 == 3'h4); endmodule |