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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-09 13:14:46 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-09 13:14:46 -0800 |
| commit | 705e520a527864dc32f1934bb4b2b94d75f8f0ec (patch) | |
| tree | 326261a49fbd7f09d53078f628cc381bd7d75939 /tests | |
| parent | a265a846324fc1699e22cad00ff23823464a84ae (diff) | |
| download | yosys-705e520a527864dc32f1934bb4b2b94d75f8f0ec.tar.gz yosys-705e520a527864dc32f1934bb4b2b94d75f8f0ec.tar.bz2 yosys-705e520a527864dc32f1934bb4b2b94d75f8f0ec.zip | |
Add a quick testcase for unknown modules as inout
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/various/submod.ys | 26 |
1 files changed, 24 insertions, 2 deletions
diff --git a/tests/various/submod.ys b/tests/various/submod.ys index 9d7dabdd7..4fb45043b 100644 --- a/tests/various/submod.ys +++ b/tests/various/submod.ys @@ -80,9 +80,8 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter - design -reset -read_verilog -icells <<EOT +read_verilog <<EOT module top(input d, c, (* init = 3'b011 *) output reg [2:0] q); (* submod="bar" *) DFF s1(.D(d), .C(c), .Q(q[1])); DFF s2(.D(d), .C(c), .Q(q[0])); @@ -100,3 +99,26 @@ proc submod dffinit -ff DFF Q INIT check -noinit -assert + + +design -reset +read_verilog <<EOT +module top(input d, c, output reg [2:0] q); +(* submod="bar" *) DFF s1(.D(d), .C(c), .Q(q[1])); +DFF s2(.D(d), .C(c), .Q(q[0])); +DFF s3(.D(d), .C(c), .Q(q[2])); +endmodule +EOT + +hierarchy -top top +proc + +submod +flatten + +read_verilog <<EOT +module DFF(input D, C, output Q); +endmodule +EOT + +check -assert |