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| author | Eddie Hung <eddie@fpgeh.com> | 2020-02-13 08:59:08 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-02-13 12:42:15 -0800 |
| commit | b523ecf2f45f80488412781ba9a3455a71d64d62 (patch) | |
| tree | 59572f382b64d2236f4bb78baffe98255bb8f485 /tests | |
| parent | 7cfdf4ffa7698fa40aae401c2b8b159a6e37011a (diff) | |
| download | yosys-b523ecf2f45f80488412781ba9a3455a71d64d62.tar.gz yosys-b523ecf2f45f80488412781ba9a3455a71d64d62.tar.bz2 yosys-b523ecf2f45f80488412781ba9a3455a71d64d62.zip | |
specify: system timing checks to accept min:typ:max triple
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/various/specify.v | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/tests/various/specify.v b/tests/various/specify.v index e4dd132f1..5006e4c38 100644 --- a/tests/various/specify.v +++ b/tests/various/specify.v @@ -44,3 +44,10 @@ specify (posedge clk *> (q +: d)) = (3,1); endspecify endmodule + +module test4(input clk, d, output q); +specify + $setup(d, posedge clk, 1:2:3); + $setuphold(d, posedge clk, 1:2:3, 4:5:6); +endspecify +endmodule |