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| author | Eddie Hung <eddie@fpgeh.com> | 2020-02-14 10:31:38 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-02-27 10:17:29 -0800 |
| commit | bc97e64b211ea4ff99afde7cd1f130b1b3261848 (patch) | |
| tree | 43145b771b0627bf2576602ac4029ab250e72029 /tests | |
| parent | 7d86aceee326d214b9e31602f00f6196d1213c9e (diff) | |
| download | yosys-bc97e64b211ea4ff99afde7cd1f130b1b3261848.tar.gz yosys-bc97e64b211ea4ff99afde7cd1f130b1b3261848.tar.bz2 yosys-bc97e64b211ea4ff99afde7cd1f130b1b3261848.zip | |
Fix tests/arch/xilinx/fsm.ys to count flops only
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/arch/xilinx/fsm.ys | 12 |
1 files changed, 3 insertions, 9 deletions
diff --git a/tests/arch/xilinx/fsm.ys b/tests/arch/xilinx/fsm.ys index fec4c6082..70c05f2c0 100644 --- a/tests/arch/xilinx/fsm.ys +++ b/tests/arch/xilinx/fsm.ys @@ -15,10 +15,7 @@ stat select -assert-count 1 t:BUFG select -assert-count 4 t:FDRE select -assert-count 1 t:FDSE -select -assert-count 1 t:LUT2 -select -assert-count 3 t:LUT5 -select -assert-count 1 t:LUT6 -select -assert-none t:BUFG t:FDRE t:FDSE t:LUT2 t:LUT5 t:LUT6 %% t:* %D +select -assert-none t:BUFG t:FDRE t:FDSE t:LUT* %% t:* %D design -load orig @@ -31,8 +28,5 @@ cd fsm # Constrain all select calls below inside the top module stat select -assert-count 1 t:BUFG select -assert-count 6 t:FDRE -select -assert-count 1 t:LUT1 -select -assert-count 3 t:LUT3 -select -assert-count 6 t:LUT4 -select -assert-count 6 t:MUXF5 -select -assert-none t:BUFG t:FDRE t:LUT1 t:LUT3 t:LUT4 t:MUXF5 %% t:* %D +# FIXME: One more register than above? +select -assert-none t:BUFG t:FDRE t:LUT* t:MUXF* %% t:* %D |