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| author | Eddie Hung <eddie@fpgeh.com> | 2020-03-11 06:51:03 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-03-11 06:51:03 -0700 |
| commit | 3ada82639ffd559da8d3f89664ac279ab2280dae (patch) | |
| tree | 39a3e48d9850e9492342167960b51ba5d11fc18f /tests | |
| parent | 2d63bf5877a99ad5a83be35b5bdc0702a947d456 (diff) | |
| download | yosys-3ada82639ffd559da8d3f89664ac279ab2280dae.tar.gz yosys-3ada82639ffd559da8d3f89664ac279ab2280dae.tar.bz2 yosys-3ada82639ffd559da8d3f89664ac279ab2280dae.zip | |
verilog: add test
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/various/src.ys | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/tests/various/src.ys b/tests/various/src.ys new file mode 100644 index 000000000..89d6700ca --- /dev/null +++ b/tests/various/src.ys @@ -0,0 +1,8 @@ +logger -expect warning "wire '\\o' is assigned in a block at <<EOT:2.11-2.17" 1 +logger -expect warning "wire '\\p' is assigned in a block at <<EOT:3.11-3.16" 1 +read_verilog <<EOT +module top(input i, output o, p); +always @* o <= i; +always @* p = i; +endmodule +EOT |