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| author | Eddie Hung <eddie@fpgeh.com> | 2020-02-13 13:27:15 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-02-13 13:27:15 -0800 |
| commit | 6b58c1820c7bbacb4730af40e10592823b0eb15c (patch) | |
| tree | f878ff9902af732ca253999dcd596f6f987cc336 /tests | |
| parent | 2e51dc1856aae456e15cafd484997bfbd102175e (diff) | |
| download | yosys-6b58c1820c7bbacb4730af40e10592823b0eb15c.tar.gz yosys-6b58c1820c7bbacb4730af40e10592823b0eb15c.tar.bz2 yosys-6b58c1820c7bbacb4730af40e10592823b0eb15c.zip | |
verilog: improve specify support when not in -specify mode
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/various/specify.v | 2 | ||||
| -rw-r--r-- | tests/various/specify.ys | 2 |
2 files changed, 1 insertions, 3 deletions
diff --git a/tests/various/specify.v b/tests/various/specify.v index aa8aca4bc..5655ded21 100644 --- a/tests/various/specify.v +++ b/tests/various/specify.v @@ -7,11 +7,9 @@ module test ( if (EN) Q <= D; specify -`ifndef SKIP_UNSUPPORTED_IGN_PARSER_CONSTRUCTS if (EN) (posedge CLK *> (Q : D)) = (1, 2:3:4); $setup(D, posedge CLK &&& EN, 5); $hold(posedge CLK, D &&& EN, 6); -`endif endspecify endmodule diff --git a/tests/various/specify.ys b/tests/various/specify.ys index 00597e1e2..a2b6038e4 100644 --- a/tests/various/specify.ys +++ b/tests/various/specify.ys @@ -55,4 +55,4 @@ equiv_induct -seq 5 equiv_status -assert design -reset -read_verilog -DSKIP_UNSUPPORTED_IGN_PARSER_CONSTRUCTS specify.v +read_verilog specify.v |