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| author | Eddie Hung <eddie@fpgeh.com> | 2020-03-02 12:32:27 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-03-02 12:32:27 -0800 |
| commit | 4f889b2f57b732083dd4bf336a0d361f70e5b2d0 (patch) | |
| tree | 5f8e46c0273e9e9bee1d6e6a6775b3f58ec302da /tests | |
| parent | b1e248b0e6c7945870c83ac82bfb4ed8e9d8ff66 (diff) | |
| parent | 090e54569a58b26d616806337c28507d199ca43c (diff) | |
| download | yosys-4f889b2f57b732083dd4bf336a0d361f70e5b2d0.tar.gz yosys-4f889b2f57b732083dd4bf336a0d361f70e5b2d0.tar.bz2 yosys-4f889b2f57b732083dd4bf336a0d361f70e5b2d0.zip | |
Merge pull request #1724 from YosysHQ/eddie/abc9_specify
abc9: auto-generate *.lut/*.box files and arrival/required times from specify entries
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/arch/ecp5/bug1630.ys | 2 | ||||
| -rw-r--r-- | tests/arch/xilinx/bug1480.ys (renamed from tests/various/bug1480.ys) | 0 | ||||
| -rw-r--r-- | tests/simple_abc9/abc.box | 2 | ||||
| -rw-r--r-- | tests/simple_abc9/abc9.v | 7 | ||||
| -rwxr-xr-x | tests/simple_abc9/run-test.sh | 4 | ||||
| -rw-r--r-- | tests/various/pmux2shiftx.v | 2 |
6 files changed, 10 insertions, 7 deletions
diff --git a/tests/arch/ecp5/bug1630.ys b/tests/arch/ecp5/bug1630.ys index b419fb9bb..63df1ad5b 100644 --- a/tests/arch/ecp5/bug1630.ys +++ b/tests/arch/ecp5/bug1630.ys @@ -1,2 +1,2 @@ read_ilang bug1630.il.gz -abc9 -lut +/ecp5/abc9_5g.lut +abc9 -lut 4 diff --git a/tests/various/bug1480.ys b/tests/arch/xilinx/bug1480.ys index 84faea08a..84faea08a 100644 --- a/tests/various/bug1480.ys +++ b/tests/arch/xilinx/bug1480.ys diff --git a/tests/simple_abc9/abc.box b/tests/simple_abc9/abc.box deleted file mode 100644 index a8801d807..000000000 --- a/tests/simple_abc9/abc.box +++ /dev/null @@ -1,2 +0,0 @@ -MUXF8 1 0 3 1 -1 1 1 diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v index e5837d480..688b47586 100644 --- a/tests/simple_abc9/abc9.v +++ b/tests/simple_abc9/abc9.v @@ -213,8 +213,13 @@ module arbiter (clk, rst, request, acknowledge, grant, grant_valid, grant_encode input rst; endmodule -(* abc9_box_id=1, whitebox *) +(* abc9_box, blackbox *) module MUXF8(input I0, I1, S, output O); +specify + (I0 => O) = 0; + (I1 => O) = 0; + (S => O) = 0; +endspecify endmodule // Citation: https://github.com/alexforencich/verilog-ethernet diff --git a/tests/simple_abc9/run-test.sh b/tests/simple_abc9/run-test.sh index 32d7a80ca..424d8f417 100755 --- a/tests/simple_abc9/run-test.sh +++ b/tests/simple_abc9/run-test.sh @@ -25,8 +25,8 @@ exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v *.sv EXTRA_FLAGS="-n 300 -p synth -run coarse; \ opt -full; \ techmap; \ - abc9 -lut 4 -box ../abc.box; \ + abc9 -lut 4; \ clean; \ check -assert; \ select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_ %%; \ - setattr -mod -unset whitebox'" + setattr -mod -unset blackbox'" diff --git a/tests/various/pmux2shiftx.v b/tests/various/pmux2shiftx.v index 563394080..c1994e92c 100644 --- a/tests/various/pmux2shiftx.v +++ b/tests/various/pmux2shiftx.v @@ -33,7 +33,7 @@ module pmux2shiftx_test ( end endmodule -module issue01135(input [7:0] i, output o); +module issue01135(input [7:0] i, output reg o); always @* case (i[6:3]) 4: o <= i[0]; |