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| author | Claire Wolf <clifford@clifford.at> | 2020-03-26 19:03:37 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-03-26 19:03:37 +0100 |
| commit | 590d8eccb7d2c58de27ecc7f9ac71cd226b1be29 (patch) | |
| tree | 13cef42d519710d93cf200b926325476512c317b /tests | |
| parent | c9555c9adeba886a308c60615ac794ec20d9276e (diff) | |
| parent | c2bf11e42a6de3f028ad0b484eb24b70618c6fc7 (diff) | |
| download | yosys-590d8eccb7d2c58de27ecc7f9ac71cd226b1be29.tar.gz yosys-590d8eccb7d2c58de27ecc7f9ac71cd226b1be29.tar.bz2 yosys-590d8eccb7d2c58de27ecc7f9ac71cd226b1be29.zip | |
Merge pull request #1806 from YosysHQ/mwk/techmap-replace-fix
techmap: Fix cell names with _TECHMAP_REPLACE_.*
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/techmap/techmap_replace.ys | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/tests/techmap/techmap_replace.ys b/tests/techmap/techmap_replace.ys index c2f42d50b..8403586bd 100644 --- a/tests/techmap/techmap_replace.ys +++ b/tests/techmap/techmap_replace.ys @@ -16,3 +16,21 @@ EOT techmap -map %techmap select -assert-any w:s0.asdf select -assert-any c:s0.blah + +read_verilog <<EOT +module sub(input i, output o, input j); +wire _TECHMAP_REPLACE_.asdf = i ; +barfoo _TECHMAP_REPLACE_.blah (i, o, j); +endmodule +EOT +design -stash techmap + +read_verilog <<EOT +module top(input i, output o); +sub s0(i, o); +endmodule +EOT + +techmap -map %techmap +select -assert-any w:s0.asdf +select -assert-any c:s0.blah |