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authorMarcin Koƛcielnicki <mwk@0x04.net>2020-03-23 11:07:03 +0100
committerMarcin Koƛcielnicki <mwk@0x04.net>2020-03-23 11:17:07 +0100
commitc2bf11e42a6de3f028ad0b484eb24b70618c6fc7 (patch)
tree5317db086bc5ba02a10f82ebec823893e00d30bc /tests
parentbeab15b77c2b279e6ebd7996d543e28334f5da20 (diff)
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techmap: Fix cell names with _TECHMAP_REPLACE_.*
Fixes #1804.
Diffstat (limited to 'tests')
-rw-r--r--tests/techmap/techmap_replace.ys18
1 files changed, 18 insertions, 0 deletions
diff --git a/tests/techmap/techmap_replace.ys b/tests/techmap/techmap_replace.ys
index c2f42d50b..8403586bd 100644
--- a/tests/techmap/techmap_replace.ys
+++ b/tests/techmap/techmap_replace.ys
@@ -16,3 +16,21 @@ EOT
techmap -map %techmap
select -assert-any w:s0.asdf
select -assert-any c:s0.blah
+
+read_verilog <<EOT
+module sub(input i, output o, input j);
+wire _TECHMAP_REPLACE_.asdf = i ;
+barfoo _TECHMAP_REPLACE_.blah (i, o, j);
+endmodule
+EOT
+design -stash techmap
+
+read_verilog <<EOT
+module top(input i, output o);
+sub s0(i, o);
+endmodule
+EOT
+
+techmap -map %techmap
+select -assert-any w:s0.asdf
+select -assert-any c:s0.blah