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* Add CHANGELOG entry, add abc9_{flop,keep} attr to README.mdEddie Hung2019-12-301-0/+6
* Put specify/endspecify inside ``Eddie Hung2019-12-201-4/+4
* Update README.md :: abc_ -> abc9_Eddie Hung2019-12-111-3/+3
* clkbufmap: Add support for inverters in clock path.Marcin Kościelnicki2019-11-251-0/+7
* Update CHANGELOG and READMEDavid Shah2019-11-221-0/+5
* Update CHANGELOG and READMEDavid Shah2019-10-031-0/+2
* Added extractinv passMarcin Kościelnicki2019-09-191-0/+6
* Merge pull request #1312 from YosysHQ/xaig_arrivalEddie Hung2019-09-051-8/+5
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| * Merge remote-tracking branch 'origin/master' into xaig_arrivalEddie Hung2019-08-301-14/+14
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| * \ Merge remote-tracking branch 'origin/master' into xaig_arrivalEddie Hung2019-08-301-1/+1
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| * \ \ Merge remote-tracking branch 'origin/master' into xaig_arrivalEddie Hung2019-08-281-0/+15
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| * \ \ \ Merge remote-tracking branch 'origin/master' into xaig_arrivalEddie Hung2019-08-231-3/+6
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| * | | | | Add (* abc_arrival=<int> *) docEddie Hung2019-08-201-0/+5
| * | | | | Deprecate `abc_scc_break` attributeEddie Hung2019-08-201-8/+0
* | | | | | Update README.mdClifford Wolf2019-09-051-1/+2
* | | | | | Rename conflicting wires on flatten/techmap, add "hierconn" attribute, fixes ...Clifford Wolf2019-09-051-0/+3
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* | | | | Merge pull request #1340 from YosysHQ/eddie/abc_no_cleanEddie Hung2019-08-301-17/+17
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| * | | | Group abc_* attribute doc with other attributesEddie Hung2019-08-291-17/+17
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* / | | Format `-pwires`Eddie Hung2019-08-301-1/+1
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* | | Mention clkbuf_inhibit can be overriddenEddie Hung2019-08-231-7/+8
* | | Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmapEddie Hung2019-08-231-3/+23
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| * | Make macOS depenency clearMiodrag Milanovic2019-08-231-2/+5
| * | Bump year in copyright noticeClifford Wolf2019-08-221-1/+1
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| * Clarify with 'only'Eddie Hung2019-08-191-1/+1
| * Update docEddie Hung2019-08-191-3/+4
| * Add doc for abc_* attributesEddie Hung2019-08-161-0/+16
* | README updatesMarcin Kościelnicki2019-08-131-0/+14
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* Update README to use "read" instead of "read_verilog"Clifford Wolf2019-07-291-48/+19
* Add support for reading gzip'd input filesDavid Shah2019-07-261-3/+3
* Updated FreeBSD dependencies in README.mdRoman-Parise2019-07-141-1/+1
* Add "read_verilog -pwires" feature, closes #1106Clifford Wolf2019-06-191-0/+4
* Add defaultvalue attributeClifford Wolf2019-06-191-0/+4
* README.md: Missing formatting for <tag>Tux32019-06-041-1/+1
* Refactor hierarchy wand/wor handlingClifford Wolf2019-05-281-1/+1
* update README.md with wand/wor informationStefan Biereigel2019-05-271-2/+2
* Add $stop to documentationClifford Wolf2019-05-091-3/+4
* Update READMEClifford Wolf2019-05-041-5/+1
* Add specify support to READMEClifford Wolf2019-04-231-0/+5
* Format some names using inline codeEddie Hung2019-04-231-2/+2
* Fix spellingEddie Hung2019-04-231-1/+1
* Merge pull request #905 from christian-krieg/feature/python_bindingsClifford Wolf2019-04-221-4/+5
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| * Changed filesystem dependency to boost instead of experimental std libraryBenedikt Tutzer2019-04-041-1/+1
| * Added dependencies to README and travis configurationBenedikt Tutzer2019-04-031-4/+5
* | Add "noblackbox" attributeClifford Wolf2019-04-211-1/+6
* | New behavior for front-end handling of whiteboxesClifford Wolf2019-04-201-0/+3
* | Add "whitebox" attribute, add "read_verilog -wb"Clifford Wolf2019-04-181-0/+4
* | README: fix some incorrect quoting.whitequark2019-04-151-2/+2
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* Add "hdlname" attributeClifford Wolf2019-03-261-0/+3
* Add note about test requirements in READMEFelix Vietmeyer2019-03-161-1/+4
* Only run derive on blackbox modules when ports have dynamic sizeClifford Wolf2019-03-021-0/+3
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