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| * | deminout: Don't demote inouts with unused bitsDavid Shah2020-03-041-0/+14
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | Fix partsel expr bit width handling and add test caseClaire Wolf2020-03-081-0/+4
| | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* | | rpc test: make frontend listen before launching yosys & introduce safeguard ↵N. Engelhardt2020-03-061-1/+2
| | | | | | | | | | | | if yosys errors
* | | tests: extend tests/arch/run-tests.sh for definesEddie Hung2020-03-051-3/+14
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* | | Merge pull request #1718 from boqwxp/precise_locationsClaire Wolf2020-03-032-4/+4
|\ \ \ | | | | | | | | Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes.
| * | | Change attribute search value to specify precise location instead of simple ↵Alberto Gonzalez2020-02-241-2/+2
| | | | | | | | | | | | | | | | line number.
| * | | Change attribute search value to specify precise location instead of simple ↵Alberto Gonzalez2020-02-241-2/+2
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* | | Merge pull request #1519 from YosysHQ/eddie/submod_poClaire Wolf2020-03-031-0/+124
|\ \ \ | | | | | | | | submod: several bugfixes
| * \ \ Merge branch 'master' into eddie/submod_poEddie Hung2020-02-0183-175/+2399
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| * | | | Add a quick testcase for unknown modules as inoutEddie Hung2019-12-091-2/+24
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* | | | | iopadmap: Look harder for already-present buffers. (#1731)Marcelina Kościelnicka2020-03-021-2/+21
| | | | | | | | | | | | | | | | | | | | | | | | | iopadmap: Look harder for already-present buffers. Fixes #1720.
* | | | | Merge pull request #1724 from YosysHQ/eddie/abc9_specifyEddie Hung2020-03-026-7/+10
|\ \ \ \ \ | | | | | | | | | | | | abc9: auto-generate *.lut/*.box files and arrival/required times from specify entries
| * | | | | Revert "Fix tests/arch/xilinx/fsm.ys to count flops only"Eddie Hung2020-02-271-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 68f903c6dd7403a4cf280cf71ee02d20345938b5.
| * | | | | Cleanup testsEddie Hung2020-02-272-1/+1
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| * | | | | Update bug1630.ys to use -lut 4 instead of lut fileEddie Hung2020-02-271-1/+1
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| * | | | | Fix tests/arch/xilinx/fsm.ys to count flops onlyEddie Hung2020-02-271-9/+3
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| * | | | | Update simple_abc9 testsEddie Hung2020-02-273-5/+8
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* / | | | ast: fixes #1710; do not generate RTLIL for unreachable ternaryEddie Hung2020-02-271-0/+30
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* | | | Merge pull request #1703 from YosysHQ/eddie/specify_improveEddie Hung2020-02-212-3/+47
|\ \ \ \ | | | | | | | | | | Improve specify parser
| * | | | clean: ignore specify-s inside cells when determining whether to keepEddie Hung2020-02-191-1/+20
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| * | | | verilog: ignore ranges too without -specifyEddie Hung2020-02-131-0/+7
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| * | | | verilog: improve specify support when not in -specify modeEddie Hung2020-02-132-3/+1
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| * | | | verilog: ignore '&&&' when not in -specify modeEddie Hung2020-02-131-0/+6
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| * | | | specify: system timing checks to accept min:typ:max tripleEddie Hung2020-02-131-0/+7
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| * | | | verilog: fix $specify3 checkEddie Hung2020-02-131-0/+7
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* | | | | Merge pull request #1642 from jjj11x/jjj11x/sv-enumClaire Wolf2020-02-204-1/+68
|\ \ \ \ \ | | | | | | | | | | | | Enum support
| * | | | | add attributes for enumerated values in ilangJeff Wang2020-02-172-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - information also useful for strongly-typed enums (not implemented) - resolves enum values in ilang part of #1594 - still need to output enums to VCD (or better yet FST) files
| * | | | | scoped enum testsJeff Wang2020-01-161-1/+13
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| * | | | | enum in package testJeff Wang2020-01-161-0/+3
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| * | | | | simple enum testJeff Wang2020-01-162-0/+52
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* | | | | | tests/aiger: Add missing .gitignoreMarcin Kościelnicki2020-02-151-0/+2
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* | | | | | Merge pull request #1701 from nakengelhardt/rpc-testMiodrag Milanović2020-02-143-7/+7
|\ \ \ \ \ \ | | | | | | | | | | | | | | make rpc frontend unix socket test less fragile
| * | | | | | make rpc frontend unix socket test less fragileN. Engelhardt2020-02-133-7/+7
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* | | | | | Fine tune #1699 testsEddie Hung2020-02-131-14/+14
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* | | | | | iopadmap: move \init attributes from outpad output to its inputEddie Hung2020-02-131-0/+37
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* | | | | Merge pull request #1679 from thasti/delay-parsingN. Engelhardt2020-02-131-0/+5
|\ \ \ \ \ | | | | | | | | | | | | Fix crash on wire declaration with delay
| * | | | | add testcase for #1614Stefan Biereigel2020-02-031-0/+5
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* | | | | Merge pull request #1670 from rodrigomelo9/masterEddie Hung2020-02-104-0/+137
|\ \ \ \ \ | | | | | | | | | | | | $readmem[hb] file inclusion is now relative to the Verilog file
| * | | | | Added 'set -e' into tests/memfile/run-test.shRodrigo Alejandro Melo2020-02-061-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Also added two checks for situations where the execution must fail. Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
| * | | | | Merge branch 'master' into masterRodrigo A. Melo2020-02-034-4/+84
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| * \ \ \ \ \ Merge branch 'master' of https://github.com/YosysHQ/yosysRodrigo Alejandro Melo2020-02-032-0/+136
| |\ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Solved a conflict into the CHANGELOG Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
| * | | | | | | Removed 'synth' into tests/memfile/run-test.shRodrigo Alejandro Melo2020-02-021-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
| * | | | | | | Added content1.dat into tests/memfileRodrigo Alejandro Melo2020-02-022-21/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Modified run-test.sh to use it. Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
| * | | | | | | Added tests/memfile to 'make test' with an extra testcaseRodrigo Alejandro Melo2020-02-011-16/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
| * | | | | | | Added a test for the Memory Content File inclusion using $readmembRodrigo Alejandro Melo2020-02-013-0/+63
| | |_|/ / / / | |/| | | | | | | | | | | | | | | | | | | Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
* | | | | | | xilinx: Add support for LUT RAM on LUT4-based devices.Marcin Kościelnicki2020-02-071-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are multiple other kinds of RAMs supported on these devices, but RAM16X1D is the only dual-port one. Fixes #1549
* | | | | | | xilinx: Initial support for LUT4 devices.Marcin Kościelnicki2020-02-073-1/+83
| |_|_|_|_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds support for mapping logic, including LUTs, wide LUTs, and carry chains. Fixes #1547
* | | | | | shiftx2mux: fix select out of boundsEddie Hung2020-02-052-1/+12
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* | | | | | Merge pull request #1576 from YosysHQ/eddie/opt_merge_initEddie Hung2020-02-051-0/+49
|\ \ \ \ \ \ | | | | | | | | | | | | | | opt_merge: discard \init of '$' cells with 'Q' port when merging
| * \ \ \ \ \ Merge remote-tracking branch 'origin/master' into eddie/opt_merge_initEddie Hung2020-01-2874-149/+1770
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