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| author | Eddie Hung <eddie@fpgeh.com> | 2020-02-05 14:56:26 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-02-05 14:56:26 -0800 |
| commit | 505557e93e0263b7714bd37b274923a6369278f5 (patch) | |
| tree | 4733ca0a6a5ebfef518506edde8e47ac58b45a6b /tests | |
| parent | 6eb7e925a12ea20192aa7caf7857a6742af8471e (diff) | |
| parent | a855f23f22c9e6dbba5ff17a9541a7d26342b56a (diff) | |
| download | yosys-505557e93e0263b7714bd37b274923a6369278f5.tar.gz yosys-505557e93e0263b7714bd37b274923a6369278f5.tar.bz2 yosys-505557e93e0263b7714bd37b274923a6369278f5.zip | |
Merge pull request #1576 from YosysHQ/eddie/opt_merge_init
opt_merge: discard \init of '$' cells with 'Q' port when merging
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/opt/opt_merge_init.ys | 49 |
1 files changed, 49 insertions, 0 deletions
diff --git a/tests/opt/opt_merge_init.ys b/tests/opt/opt_merge_init.ys new file mode 100644 index 000000000..a29c29df6 --- /dev/null +++ b/tests/opt/opt_merge_init.ys @@ -0,0 +1,49 @@ +read_verilog -icells <<EOT +module top(input clk, i, (* init = 1'b0 *) output o, p); + \$dff #( + .CLK_POLARITY(1'h1), + .WIDTH(32'd1) + ) ffo ( + .CLK(clk), + .D(i), + .Q(o) + ); + \$dff #( + .CLK_POLARITY(1'h1), + .WIDTH(32'd1) + ) ffp ( + .CLK(clk), + .D(i), + .Q(p) + ); +endmodule +EOT + +opt_merge +select -assert-count 1 a:init=1'0 + + +design -reset +read_verilog -icells <<EOT +module top(input clk, i, (* init = 2'b11 *) output [1:0] o); + \$dff #( + .CLK_POLARITY(1'h1), + .WIDTH(32'd1) + ) ff1 ( + .CLK(clk), + .D(i), + .Q(o[1]) + ); + \$dff #( + .CLK_POLARITY(1'h1), + .WIDTH(32'd1) + ) ff0 ( + .CLK(clk), + .D(i), + .Q(o[0]) + ); +endmodule +EOT + +opt_merge +select -assert-count 1 a:init=2'bx1 |