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* Fix typo in BEddie Hung2019-07-191-1/+1
* Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-07-1815-84/+164
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| * Merge pull request #1208 from ZirconiumX/intel_cleanupsDavid Shah2019-07-181-29/+14
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| | * synth_intel: Use stringfDan Ravensloft2019-07-181-7/+2
| | * synth_intel: s/not family/no family/Dan Ravensloft2019-07-181-2/+2
| | * intel_synth: Fix help messageBen Widawsky2019-07-181-1/+1
| | * intel_synth: Small code cleanup to remove if ladderBen Widawsky2019-07-181-28/+10
| | * intel_synth: Make family explicit and matchBen Widawsky2019-07-181-2/+6
| | * intel_synth: Minor code cleanupsBen Widawsky2019-07-181-2/+6
| * | synth_intel: rename for consistency with #1184Dan Ravensloft2019-07-181-4/+4
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| * Merge pull request #1184 from whitequark/synth-better-labelsClifford Wolf2019-07-185-17/+21
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| | * synth_ecp5: rename dram to lutram everywhere.whitequark2019-07-164-13/+13
| | * synth_{ice40,ecp5}: more sensible pass label naming.whitequark2019-07-162-5/+9
| * | Merge pull request #1204 from smunaut/fix_1187David Shah2019-07-172-4/+4
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| | * | ice40: Adapt the relut process passes to the new $lut <=> SB_LUT4 port mapSylvain Munaut2019-07-162-4/+4
| * | | gen_lut to return correctly sized LUT maskEddie Hung2019-07-161-1/+1
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| * | Merge pull request #1186 from YosysHQ/eddie/abc9_ice40_fixEddie Hung2019-07-168-29/+120
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| | * $__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequarkEddie Hung2019-07-157-8/+8
| | * ice40_opt to $__ICE40_CARRY_LUT4 into $lut not SB_LUTEddie Hung2019-07-131-9/+7
| | * Use Const::from_string() not its constructor...Eddie Hung2019-07-121-1/+1
| | * Off by oneEddie Hung2019-07-121-1/+1
| | * Fix spacingEddie Hung2019-07-121-1/+1
| | * Remove double pushEddie Hung2019-07-121-1/+0
| | * Map to and from this box if -abc9Eddie Hung2019-07-121-2/+3
| | * ice40_opt to handle this box and opt back to SB_LUT4Eddie Hung2019-07-121-0/+48
| | * Add new box to cells_sim.vEddie Hung2019-07-121-2/+25
| | * _ABC macro will map and unmap to this new boxEddie Hung2019-07-122-0/+34
| | * Combine SB_CARRY+SB_LUT into one $__ICE40_CARRY_LUT4 boxEddie Hung2019-07-123-25/+13
* | | Make consistentEddie Hung2019-07-181-1/+2
* | | Fix signed multiplier decompositionEddie Hung2019-07-181-29/+36
* | | Use single DSP_SIGNEDONLY macroEddie Hung2019-07-181-1/+1
* | | Working for unsignedEddie Hung2019-07-181-52/+28
* | | CleanupEddie Hung2019-07-181-70/+58
* | | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dspEddie Hung2019-07-181-31/+41
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| * | | mul2dsp: Lower partial products always have unsigned inputsDavid Shah2019-07-181-31/+41
* | | | Make all operands signedEddie Hung2019-07-171-1/+1
* | | | Update commentEddie Hung2019-07-171-5/+3
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* | | Fix mul2dsp signednessEddie Hung2019-07-171-42/+38
* | | A_SIGNED == B_SIGNED so flip bothEddie Hung2019-07-171-21/+12
* | | Add DSP_{A,B}_SIGNEDONLY macroEddie Hung2019-07-161-11/+40
* | | SignednessEddie Hung2019-07-162-8/+8
* | | Revert drop down to 24x16 multipliers for allEddie Hung2019-07-162-4/+4
* | | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dspEddie Hung2019-07-164-27/+35
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| * | | xilinx: Add correct signed behaviour to DSP48E1 modelDavid Shah2019-07-161-1/+1
| * | | xilinx: Treat DSP48E1 as 24x17 unsigned for now (actual behaviour is 25x18 si...David Shah2019-07-162-4/+8
| * | | mul2dsp: Fix edge case where Y_WIDTH is less than B_WIDTH+`DSP_A_MAXWIDTHDavid Shah2019-07-161-18/+22
| * | | mul2dsp: Fix indentationDavid Shah2019-07-161-7/+7
* | | | Add support for {A,B,P}REG in DSP48E1Eddie Hung2019-07-161-5/+21
* | | | Do not swap if equalsEddie Hung2019-07-151-1/+1
* | | | Oops forgot these filesEddie Hung2019-07-152-0/+5
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