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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-16 14:30:25 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-16 14:30:25 -0700 |
| commit | 6390c535ba70c0a4fe0cb08156fefa80fb621e47 (patch) | |
| tree | b56da677bd51c81143a9d1b16d9168a62641a024 /techlibs | |
| parent | 569cd66764f43af9ea73038ce7437ab8557d497e (diff) | |
| download | yosys-6390c535ba70c0a4fe0cb08156fefa80fb621e47.tar.gz yosys-6390c535ba70c0a4fe0cb08156fefa80fb621e47.tar.bz2 yosys-6390c535ba70c0a4fe0cb08156fefa80fb621e47.zip | |
Revert drop down to 24x16 multipliers for all
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/dsp_map.v | 6 | ||||
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 2 |
2 files changed, 4 insertions, 4 deletions
diff --git a/techlibs/xilinx/dsp_map.v b/techlibs/xilinx/dsp_map.v index 2063c45e2..da1d6f3a9 100644 --- a/techlibs/xilinx/dsp_map.v +++ b/techlibs/xilinx/dsp_map.v @@ -1,4 +1,4 @@ -module \$__MUL25X18 (input [23:0] A, input [16:0] B, output [40:0] Y); +module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] Y); wire [47:0] P_48; DSP48E1 #( // Disable all registers @@ -20,8 +20,8 @@ module \$__MUL25X18 (input [23:0] A, input [16:0] B, output [40:0] Y); .PREG(0) ) _TECHMAP_REPLACE_ ( //Data path - .A({6'b0, A}), - .B({1'b0, B}), + .A({5'b0, A}), + .B(B), .C(48'b0), .D(24'b0), .P(P_48), diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 815bf0848..bfce922db 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -289,7 +289,7 @@ struct SynthXilinxPass : public ScriptPass // unsigned multiply with MSBs set to 1'b0 if (!nodsp || help_mode) - run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=24 -D DSP_B_MAXWIDTH=17 -D DSP_NAME=$__MUL25X18"); + run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=25 -D DSP_A_SIGNEDONLY=1 -D DSP_B_MAXWIDTH=18 -D DSP_B_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18"); run("alumacc"); run("share"); |