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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-17 12:44:52 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-17 12:44:52 -0700 |
| commit | 8dca8d486e945eb5883e6757f711011ed23aa5ba (patch) | |
| tree | 48d84b863772bf832dff1d3bd7b08481530c57b9 /techlibs | |
| parent | 1b62b82e05ef5405d8ddff211f623d90d848a9ca (diff) | |
| download | yosys-8dca8d486e945eb5883e6757f711011ed23aa5ba.tar.gz yosys-8dca8d486e945eb5883e6757f711011ed23aa5ba.tar.bz2 yosys-8dca8d486e945eb5883e6757f711011ed23aa5ba.zip | |
Fix mul2dsp signedness
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/common/mul2dsp.v | 80 |
1 files changed, 38 insertions, 42 deletions
diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index d19599620..7344bc5fe 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -34,49 +34,45 @@ module \$mul (A, B, Y); output [Y_WIDTH-1:0] Y;
generate
- localparam add_sign_A = `DSP_A_SIGNEDONLY && !A_SIGNED;
- localparam add_sign_B = `DSP_B_SIGNEDONLY && !B_SIGNED;
- if (add_sign_A || add_sign_B) begin
- if (add_sign_A && add_sign_B)
- wire [1:0] dummy;
- else
- wire dummy;
- \$mul #(
- .A_SIGNED(1),
- .B_SIGNED(1),
- .A_WIDTH(A_WIDTH + (add_sign_A ? 1 : 0)),
- .B_WIDTH(B_WIDTH + (add_sign_B ? 1 : 0)),
- .Y_WIDTH(Y_WIDTH + (add_sign_A ? 1 : 0) + (add_sign_B ? 1 : 0))
- ) _TECHMAP_REPLACE_ (
- .A(add_sign_A ? {1'b0, A} : A),
- .B(add_sign_B ? {1'b0, B} : B),
- .Y({dummy, Y})
- );
+ if (`DSP_A_SIGNEDONLY && `DSP_B_SIGNEDONLY && !A_SIGNED) begin
+ wire [1:0] dummy;
+ \$mul #(
+ .A_SIGNED(1),
+ .B_SIGNED(1),
+ .A_WIDTH(A_WIDTH + 1),
+ .B_WIDTH(B_WIDTH + 1),
+ .Y_WIDTH(Y_WIDTH + 2)
+ ) _TECHMAP_REPLACE_ (
+ .A({1'b0, A}),
+ .B({1'b0, B}),
+ .Y({dummy, Y})
+ );
end
- else if (A_WIDTH >= B_WIDTH)
- \$__mul_gen #(
- .A_SIGNED(A_SIGNED),
- .B_SIGNED(B_SIGNED),
- .A_WIDTH(A_WIDTH),
- .B_WIDTH(B_WIDTH),
- .Y_WIDTH(Y_WIDTH)
- ) _TECHMAP_REPLACE_ (
- .A(A),
- .B(B),
- .Y(Y)
- );
- else
- \$__mul_gen #(
- .A_SIGNED(B_SIGNED),
- .B_SIGNED(A_SIGNED),
- .A_WIDTH(B_WIDTH),
- .B_WIDTH(A_WIDTH),
- .Y_WIDTH(Y_WIDTH)
- ) _TECHMAP_REPLACE_ (
- .A(B),
- .B(A),
- .Y(Y)
- );
+ // NB: A_SIGNED == B_SIGNED == 0 from here
+ else if (A_WIDTH >= B_WIDTH)
+ \$__mul_gen #(
+ .A_SIGNED(A_SIGNED),
+ .B_SIGNED(B_SIGNED),
+ .A_WIDTH(A_WIDTH),
+ .B_WIDTH(B_WIDTH),
+ .Y_WIDTH(Y_WIDTH)
+ ) _TECHMAP_REPLACE_ (
+ .A(A),
+ .B(B),
+ .Y(Y)
+ );
+ else
+ \$__mul_gen #(
+ .A_SIGNED(B_SIGNED),
+ .B_SIGNED(A_SIGNED),
+ .A_WIDTH(B_WIDTH),
+ .B_WIDTH(A_WIDTH),
+ .Y_WIDTH(Y_WIDTH)
+ ) _TECHMAP_REPLACE_ (
+ .A(B),
+ .B(A),
+ .Y(Y)
+ );
endgenerate
endmodule
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