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| author | David Shah <dave@ds0.me> | 2019-07-17 07:55:26 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-07-17 07:55:26 +0100 |
| commit | 82153059a1ba0fa64086a82fd5ae68f01b983e55 (patch) | |
| tree | af49b37c03d027500aef49419fb8420decb539b4 /techlibs | |
| parent | f8e470c1d1178680034a28a9f28b161acf667701 (diff) | |
| parent | f28e38de9994151ea4e22608441dbc9e116d7b8c (diff) | |
| download | yosys-82153059a1ba0fa64086a82fd5ae68f01b983e55.tar.gz yosys-82153059a1ba0fa64086a82fd5ae68f01b983e55.tar.bz2 yosys-82153059a1ba0fa64086a82fd5ae68f01b983e55.zip | |
Merge pull request #1204 from smunaut/fix_1187
ice40: Adapt the relut process passes to the new $lut/SB_LUT4 port map
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/ice40/ice40_unlut.cc | 6 | ||||
| -rw-r--r-- | techlibs/ice40/synth_ice40.cc | 2 |
2 files changed, 4 insertions, 4 deletions
diff --git a/techlibs/ice40/ice40_unlut.cc b/techlibs/ice40/ice40_unlut.cc index d16e6e6a3..f3f70ac1f 100644 --- a/techlibs/ice40/ice40_unlut.cc +++ b/techlibs/ice40/ice40_unlut.cc @@ -56,10 +56,10 @@ static void run_ice40_unlut(Module *module) cell->unsetParam("\\LUT_INIT"); cell->setPort("\\A", SigSpec({ - get_bit_or_zero(cell->getPort("\\I3")), - get_bit_or_zero(cell->getPort("\\I2")), + get_bit_or_zero(cell->getPort("\\I0")), get_bit_or_zero(cell->getPort("\\I1")), - get_bit_or_zero(cell->getPort("\\I0")) + get_bit_or_zero(cell->getPort("\\I2")), + get_bit_or_zero(cell->getPort("\\I3")) })); cell->setPort("\\Y", cell->getPort("\\O")[0]); cell->unsetPort("\\I0"); diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index b3d30791a..78ac5ea13 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -345,7 +345,7 @@ struct SynthIce40Pass : public ScriptPass } run("clean"); run("ice40_unlut"); - run("opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3"); + run("opt_lut -dlogic SB_CARRY:I0=2:I1=1:CI=0"); } if (check_label("map_cells")) |