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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-13 01:11:00 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-13 01:11:00 -0700 |
| commit | d032198facc05634bd617328e1865e7f0d8d953c (patch) | |
| tree | 96f90336e317cdc8885fb30eb75f294079f165b8 /techlibs | |
| parent | 7dc15bdd2dff8493ee5786845a5e39427bf3779d (diff) | |
| download | yosys-d032198facc05634bd617328e1865e7f0d8d953c.tar.gz yosys-d032198facc05634bd617328e1865e7f0d8d953c.tar.bz2 yosys-d032198facc05634bd617328e1865e7f0d8d953c.zip | |
ice40_opt to $__ICE40_CARRY_LUT4 into $lut not SB_LUT
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/ice40/ice40_opt.cc | 16 |
1 files changed, 7 insertions, 9 deletions
diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc index 67e8771b4..38910dffa 100644 --- a/techlibs/ice40/ice40_opt.cc +++ b/techlibs/ice40/ice40_opt.cc @@ -114,19 +114,17 @@ static void run_ice40_opts(Module *module) optimized_co.insert(sigmap(cell->getPort("\\CO")[0])); module->connect(cell->getPort("\\CO")[0], replacement_output); module->design->scratchpad_set_bool("opt.did_something", true); - log("Optimized SB_CARRY from $__ICE40_CARRY_LUT4 cell (leaving behind SB_LUT4) %s.%s: CO=%s\n", + log("Optimized $__ICE40_CARRY_LUT4 cell into $lut (without SB_CARRY) %s.%s: CO=%s\n", log_id(module), log_id(cell), log_signal(replacement_output)); - cell->type = "\\SB_LUT4"; - cell->setPort("\\I0", RTLIL::S0); - cell->setPort("\\I1", inbit[0]); - cell->setPort("\\I2", inbit[1]); - cell->setPort("\\I3", inbit[2]); - cell->unsetPort("\\A"); + cell->type = "$lut"; + cell->setPort("\\A", { RTLIL::S0, inbit[0], inbit[1], inbit[2] }); + cell->setPort("\\Y", cell->getPort("\\O")); cell->unsetPort("\\B"); cell->unsetPort("\\CI"); cell->unsetPort("\\CO"); - cell->setParam("\\LUT_INIT", RTLIL::Const::from_string("0110100110010110")); - sb_lut_cells.push_back(cell); + cell->unsetPort("\\O"); + cell->setParam("\\LUT", RTLIL::Const::from_string("0110100110010110")); + cell->setParam("\\WIDTH", 4); } continue; } |