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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-15 16:52:37 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-15 16:52:37 -0700 |
| commit | fd5b3593d8496578c0879fc024bf81737be3702f (patch) | |
| tree | 5ccda43899311d0fb4d033e726dce5af691ad678 /techlibs | |
| parent | b29f26f6c7d880b9a446f6eacfa988c2018a1e30 (diff) | |
| download | yosys-fd5b3593d8496578c0879fc024bf81737be3702f.tar.gz yosys-fd5b3593d8496578c0879fc024bf81737be3702f.tar.bz2 yosys-fd5b3593d8496578c0879fc024bf81737be3702f.zip | |
Do not swap if equals
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/common/mul2dsp.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 0a87716d9..046f84320 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -33,7 +33,7 @@ module \$mul (A, B, Y); output [Y_WIDTH-1:0] Y;
generate
- if (B_WIDTH < A_WIDTH)
+ if (A_WIDTH >= B_WIDTH)
\$__mul_gen #(
.A_SIGNED(A_SIGNED),
.B_SIGNED(B_SIGNED),
|