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authorDan Ravensloft <dan.ravensloft@gmail.com>2019-07-18 16:46:21 +0100
committerDan Ravensloft <dan.ravensloft@gmail.com>2019-07-18 16:46:21 +0100
commitc78ab8ebc53bc78d5f1910e311b1e4305df4ca48 (patch)
tree624d9007295dd7f50ed5b30717016ec0098464ed /techlibs
parente66e8fb59d8443c8d55c1185d6b2ce889a35357d (diff)
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synth_intel: rename for consistency with #1184
Also fix a typo in the help message.
Diffstat (limited to 'techlibs')
-rw-r--r--techlibs/intel/synth_intel.cc8
1 files changed, 4 insertions, 4 deletions
diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc
index 09c9ba3af..4f355ce88 100644
--- a/techlibs/intel/synth_intel.cc
+++ b/techlibs/intel/synth_intel.cc
@@ -62,10 +62,10 @@ struct SynthIntelPass : public ScriptPass {
log(" synonymous to the end of the command list.\n");
log("\n");
log(" -noiopads\n");
- log(" do not use altsyncram cells in output netlist\n");
+ log(" do not use IO pad cells in output netlist\n");
log("\n");
log(" -nobram\n");
- log(" do not use altsyncram cells in output netlist\n");
+ log(" do not use block RAM cells in output netlist\n");
log("\n");
log(" -noflatten\n");
log(" do not flatten design before synthesis\n");
@@ -191,12 +191,12 @@ struct SynthIntelPass : public ScriptPass {
run("synth -run coarse");
}
- if (!nobram && check_label("bram", "(skip if -nobram)")) {
+ if (!nobram && check_label("map_bram", "(skip if -nobram)")) {
run("memory_bram -rules +/intel/common/brams.txt");
run("techmap -map +/intel/common/brams_map.v");
}
- if (check_label("fine")) {
+ if (check_label("map_ffram")) {
run("opt -fast -mux_undef -undriven -fine -full");
run("memory_map");
run("opt -undriven -fine");