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| author | David Shah <dave@ds0.me> | 2019-07-16 17:53:08 +0100 |
|---|---|---|
| committer | David Shah <dave@ds0.me> | 2019-07-16 17:53:08 +0100 |
| commit | d38df68d26f1644539e5116e6b6c360e1c389cc9 (patch) | |
| tree | 9fdb7f6af418e0f6ce36818a2f53aab08cf16c46 /techlibs | |
| parent | 95c8d27b0bfdea330a62a18825dea3691b4affe2 (diff) | |
| download | yosys-d38df68d26f1644539e5116e6b6c360e1c389cc9.tar.gz yosys-d38df68d26f1644539e5116e6b6c360e1c389cc9.tar.bz2 yosys-d38df68d26f1644539e5116e6b6c360e1c389cc9.zip | |
xilinx: Add correct signed behaviour to DSP48E1 model
Signed-off-by: David Shah <dave@ds0.me>
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 99120452c..ea5a3b788 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -506,6 +506,6 @@ module DSP48E1 ( if (PCIN != 48'b0) $fatal(1, "Unsupported PCIN value"); if (CARRYIN != 1'b0) $fatal(1, "Unsupported CARRYIN value"); `endif - P[42:0] <= A[24:0] * B; + P[42:0] <= $signed(A[24:0]) * $signed(B); end endmodule |