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authorDavid Shah <dave@ds0.me>2019-07-16 16:46:41 +0100
committerDavid Shah <dave@ds0.me>2019-07-16 16:47:53 +0100
commit95c8d27b0bfdea330a62a18825dea3691b4affe2 (patch)
tree930265835858e9f5068b0c50766b6f6e4d855237 /techlibs
parent8da4c1ad8262216c5204c735f5297da33fed01fa (diff)
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xilinx: Treat DSP48E1 as 24x17 unsigned for now (actual behaviour is 25x18 signed)
Signed-off-by: David Shah <dave@ds0.me>
Diffstat (limited to 'techlibs')
-rw-r--r--techlibs/xilinx/cells_map.v6
-rw-r--r--techlibs/xilinx/synth_xilinx.cc6
2 files changed, 8 insertions, 4 deletions
diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index 6ebca0d54..8302e0b3a 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -366,7 +366,7 @@ module \$__XILINX_MUXF78 (O, I0, I1, I2, I3, S0, S1);
endmodule
`endif
-module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] OUT);
+module \$__MUL25X18 (input [23:0] A, input [16:0] B, output [40:0] OUT);
wire [47:0] P_48;
DSP48E1 #(
// Disable all registers
@@ -388,8 +388,8 @@ module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] OUT);
.PREG(0)
) _TECHMAP_REPLACE_ (
//Data path
- .A({5'b0, A}),
- .B(B),
+ .A({6'b0, A}),
+ .B({1'b0, B}),
.C(48'b0),
.D(24'b0),
.P(P_48),
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 01e75b50e..5bfbd1583 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -284,8 +284,12 @@ struct SynthXilinxPass : public ScriptPass
run("techmap -map +/cmp2lut.v -D LUT_WIDTH=6");
+ // The actual behaviour of the Xilinx DSP is a signed 25x18 multiply
+ // Due to current limitations of mul2dsp, we are actually mapping as a 24x17
+ // unsigned multiply with MSBs set to 1'b0
+
if (!nodsp || help_mode)
- run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=25 -D DSP_B_MAXWIDTH=18 -D DSP_NAME=$__MUL25X18");
+ run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=24 -D DSP_B_MAXWIDTH=17 -D DSP_NAME=$__MUL25X18");
run("alumacc");
run("share");