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* greenpak4: Cleaned up trailing spaces in cells_simAndrew Zonenberg2016-12-141-60/+60
* greenpak4: Added GP_DCMPREF / GP_DCMPMUXAndrew Zonenberg2016-12-141-0/+23
* Added GP_PWRDET block, BANDWIDTH_KHZ parameter to GP_ABUFAndrew Zonenberg2016-12-111-1/+9
* greenpak4: Added support for inferred input/output inverters on latchesAndrew Zonenberg2016-12-101-4/+17
* greenpak4: Can now techmap inferred D latches (without set/reset or output in...Andrew Zonenberg2016-12-103-0/+17
* greenpak4: Inverted D latch cells now have nQ instead of Q as output port nam...Andrew Zonenberg2016-12-101-15/+15
* Added GP_DLATCH and GP_DLATCHIAndrew Zonenberg2016-12-051-0/+18
* Initial implementation of techlib support for GreenPAK latches. Instantiation...Andrew Zonenberg2016-12-052-0/+120
* Updated help text for synth_greenpak4Andrew Zonenberg2016-12-051-0/+2
* Indenting fixes in gowin sim cell libClifford Wolf2016-11-081-20/+28
* Added hex constant support to write_verilogClifford Wolf2016-11-031-1/+1
* iCE40 flow is not experimental anymoreClifford Wolf2016-11-011-1/+1
* Added initial version of "synth_gowin"Clifford Wolf2016-11-014-0/+266
* Fixed typo in last commitAndrew Zonenberg2016-10-181-1/+1
* greenpak4: Added GP_PGEN cell definitionAndrew Zonenberg2016-10-181-0/+21
* Added GLITCH_FILTER parameter to GP_DELAYAndrew Zonenberg2016-10-181-3/+2
* greenpak4: added model for GP_EDGEDET blockAndrew Zonenberg2016-10-181-0/+10
* greenpak4: Changed parameters for GP_SYSRESETAndrew Zonenberg2016-10-161-1/+2
* Added $anyseq cell typeClifford Wolf2016-10-141-0/+12
* Added $global_clock verilog syntax support for creating $ff cellsClifford Wolf2016-10-142-2/+23
* Added $ff and $_FF_ cell typesClifford Wolf2016-10-122-1/+14
* Added "prep -nokeepdc"Clifford Wolf2016-09-301-4/+12
* Added "prep -nomem"Clifford Wolf2016-08-301-6/+16
* Removed $aconst cell typeClifford Wolf2016-08-301-12/+0
* Removed $predict againClifford Wolf2016-08-281-8/+0
* Added "wreduce -memx"Clifford Wolf2016-08-201-2/+6
* Added memory_memx pass, "memory -memx", and "prep -memx"Clifford Wolf2016-08-191-2/+17
* Added greenpak4_dffinvClifford Wolf2016-08-153-0/+199
* greenpak4: Changed name of inverted output ports for consistencyAndrew Zonenberg2016-08-142-19/+19
* greenpak4: Added GP_DFFxI cellsAndrew Zonenberg2016-08-142-0/+68
* greenpak4: Renamed ports for better consistency (see azonenberg/openfpga:#6)Andrew Zonenberg2016-08-131-10/+10
* synth_greenpak4: use attrmvcp to move LOC from wires to cells.whitequark2016-08-101-0/+2
* Added $anyconst and $aconstClifford Wolf2016-07-271-0/+24
* Added $initstate cell type and vlog functionClifford Wolf2016-07-211-0/+17
* After reading the SV spec, using non-standard predict() instead of expect()Clifford Wolf2016-07-211-9/+1
* Added basic support for $expect cellsClifford Wolf2016-07-131-0/+16
* Added GP_DAC cellAndrew Zonenberg2016-07-111-0/+8
* Removed VOUT port of GP_BANDGAPAndrew Zonenberg2016-07-111-1/+1
* Removed splitnets in prep for new gp4par parserAndrew Zonenberg2016-07-111-1/+0
* Added "prep -auto-top" and "synth -auto-top"Clifford Wolf2016-07-112-6/+23
* greenpak4: add GP_COUNT{8,14}_ADV cells.whitequark2016-07-101-0/+26
* Minor fixes in ice40_ff* passes for sloppy SB_DFF instantiationsClifford Wolf2016-07-082-13/+24
* Improved ice40_ffinit error reportingClifford Wolf2016-06-301-1/+5
* Added "deminout"Clifford Wolf2016-06-191-0/+1
* Improved support for $sop cellsClifford Wolf2016-06-172-4/+4
* Added $sop cell type and "abc -sop"Clifford Wolf2016-06-171-0/+28
* Added "nlutmap -assert"Clifford Wolf2016-06-091-3/+3
* Do not run "wreduce" in "prep -ifx"Clifford Wolf2016-06-081-2/+3
* Added "proc_mux -ifx"Clifford Wolf2016-06-061-2/+11
* Added GP_DELAY cellAndrew Zonenberg2016-05-071-0/+29
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