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| author | Clifford Wolf <clifford@clifford.at> | 2016-08-28 21:35:33 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-08-28 21:35:33 +0200 |
| commit | eae390ae17839bf0273b32149f46a2560a23d934 (patch) | |
| tree | 218b3327ef63938a762859386f23215cef83c4d3 /techlibs | |
| parent | 66582964bc11aadf3d0783a346706d801451a13f (diff) | |
| download | yosys-eae390ae17839bf0273b32149f46a2560a23d934.tar.gz yosys-eae390ae17839bf0273b32149f46a2560a23d934.tar.bz2 yosys-eae390ae17839bf0273b32149f46a2560a23d934.zip | |
Removed $predict again
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/common/simlib.v | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index ac4269c90..d0a6cd495 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -1305,14 +1305,6 @@ endmodule // -------------------------------------------------------- -module \$predict (A, EN); - -input A, EN; - -endmodule - -// -------------------------------------------------------- - module \$initstate (Y); output reg Y = 1; |