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| author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-07-11 22:45:55 -0700 |
|---|---|---|
| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-07-11 22:45:55 -0700 |
| commit | 52a738a54435d9e54ac7cb523551ae866cc76770 (patch) | |
| tree | eb8241fc32d0204461f77b41b95d52a479dbf370 /techlibs | |
| parent | baae472b83b3dac1293bb95ff0a87d9180a67479 (diff) | |
| download | yosys-52a738a54435d9e54ac7cb523551ae866cc76770.tar.gz yosys-52a738a54435d9e54ac7cb523551ae866cc76770.tar.bz2 yosys-52a738a54435d9e54ac7cb523551ae866cc76770.zip | |
Added GP_DAC cell
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/greenpak4/cells_sim.v | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index bf178a08a..ca8556a85 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -120,6 +120,14 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT, endmodule +module GP_DAC(input[7:0] DIN, input wire VREF, output reg VOUT); + + initial VOUT = 0; + + //analog hard IP is not supported for simulation + +endmodule + module GP_DELAY(input IN, output reg OUT); parameter DELAY_STEPS = 1; |