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| author | Clifford Wolf <clifford@clifford.at> | 2016-11-01 11:32:02 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-11-01 11:32:02 +0100 |
| commit | 81bdf0ad0f36573945bc27d1a9cdd2e4925bf085 (patch) | |
| tree | c253b21f2c531da43686bb2703821eb9d63a2fd0 /techlibs | |
| parent | cae5131bace469ca9c6ecde9fb51f2d8ec6643bc (diff) | |
| download | yosys-81bdf0ad0f36573945bc27d1a9cdd2e4925bf085.tar.gz yosys-81bdf0ad0f36573945bc27d1a9cdd2e4925bf085.tar.bz2 yosys-81bdf0ad0f36573945bc27d1a9cdd2e4925bf085.zip | |
iCE40 flow is not experimental anymore
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/ice40/synth_ice40.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 38a9cf9d6..2533d3af8 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -35,7 +35,7 @@ struct SynthIce40Pass : public ScriptPass log("\n"); log(" synth_ice40 [options]\n"); log("\n"); - log("This command runs synthesis for iCE40 FPGAs. This work is experimental.\n"); + log("This command runs synthesis for iCE40 FPGAs.\n"); log("\n"); log(" -top <module>\n"); log(" use the specified module as top module (default='top')\n"); |