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| author | Clifford Wolf <clifford@clifford.at> | 2016-06-17 16:31:16 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-06-17 16:31:16 +0200 |
| commit | 95757efb25dc51a73b384b475b0fc87d0e11d10e (patch) | |
| tree | b0c4518d676e8389629ca96482231616232add14 /techlibs | |
| parent | 52bb1b968d4bfbbbd84eca88f0e80c486cc1a16e (diff) | |
| download | yosys-95757efb25dc51a73b384b475b0fc87d0e11d10e.tar.gz yosys-95757efb25dc51a73b384b475b0fc87d0e11d10e.tar.bz2 yosys-95757efb25dc51a73b384b475b0fc87d0e11d10e.zip | |
Improved support for $sop cells
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/common/simlib.v | 6 | ||||
| -rw-r--r-- | techlibs/common/techmap.v | 2 |
2 files changed, 4 insertions, 4 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index 493292582..342555024 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -1340,7 +1340,7 @@ wire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR; genvar i; generate - for (i = 0; i < WIDTH; i = i+1) begin:bit + for (i = 0; i < WIDTH; i = i+1) begin:bitslices always @(posedge pos_set[i], posedge pos_clr[i]) if (pos_clr[i]) Q[i] <= 0; @@ -1409,7 +1409,7 @@ wire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR; genvar i; generate - for (i = 0; i < WIDTH; i = i+1) begin:bit + for (i = 0; i < WIDTH; i = i+1) begin:bitslices always @(posedge pos_set[i], posedge pos_clr[i], posedge pos_clk) if (pos_clr[i]) Q[i] <= 0; @@ -1485,7 +1485,7 @@ wire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR; genvar i; generate - for (i = 0; i < WIDTH; i = i+1) begin:bit + for (i = 0; i < WIDTH; i = i+1) begin:bitslices always @* if (pos_clr[i]) Q[i] = 0; diff --git a/techlibs/common/techmap.v b/techlibs/common/techmap.v index a623bb516..90c4ed7eb 100644 --- a/techlibs/common/techmap.v +++ b/techlibs/common/techmap.v @@ -452,7 +452,7 @@ endmodule `ifndef NOLUT (* techmap_simplemap *) -(* techmap_celltype = "$lut" *) +(* techmap_celltype = "$lut $sop" *) module _90_lut; endmodule `endif |