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| author | Clifford Wolf <clifford@clifford.at> | 2016-10-14 15:24:03 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-10-14 15:24:03 +0200 |
| commit | bdc316db50cd8b68ef096386a89c1b38793784e1 (patch) | |
| tree | 507341053afa28df1a753ef9de33c3d096683720 /techlibs | |
| parent | 2733994aeba0879533cc1a871aae84497b32ff9e (diff) | |
| download | yosys-bdc316db50cd8b68ef096386a89c1b38793784e1.tar.gz yosys-bdc316db50cd8b68ef096386a89c1b38793784e1.tar.bz2 yosys-bdc316db50cd8b68ef096386a89c1b38793784e1.zip | |
Added $anyseq cell type
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/common/simlib.v | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index b10c858f2..2c4db1ac6 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -1334,6 +1334,18 @@ endmodule // -------------------------------------------------------- +module \$anyseq (Y); + +parameter WIDTH = 0; + +output [WIDTH-1:0] Y; + +assign Y = 'bx; + +endmodule + +// -------------------------------------------------------- + module \$equiv (A, B, Y); input A, B; |