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| author | Clifford Wolf <clifford@clifford.at> | 2016-07-21 13:34:33 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-07-21 13:34:33 +0200 |
| commit | d7763634b68a735443c61aa32918ee0cdd6e9250 (patch) | |
| tree | d04a1d072d727d0776c42f68668785403cc92bf5 /techlibs | |
| parent | 721f1f5ecfb6334904f6058d6d376d21b5efc438 (diff) | |
| download | yosys-d7763634b68a735443c61aa32918ee0cdd6e9250.tar.gz yosys-d7763634b68a735443c61aa32918ee0cdd6e9250.tar.bz2 yosys-d7763634b68a735443c61aa32918ee0cdd6e9250.zip | |
After reading the SV spec, using non-standard predict() instead of expect()
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/common/simlib.v | 10 |
1 files changed, 1 insertions, 9 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index ea36e2922..38687489a 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -1305,18 +1305,10 @@ endmodule // -------------------------------------------------------- -module \$expect (A, EN); +module \$predict (A, EN); input A, EN; -`ifndef SIMLIB_NOCHECKS -always @* begin - if (A === 1'b1 && EN === 1'b1) begin - $display("Expectation %m passed."); - end -end -`endif - endmodule // -------------------------------------------------------- |