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| author | Clifford Wolf <clifford@clifford.at> | 2016-07-13 16:56:17 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-07-13 16:56:17 +0200 |
| commit | 721f1f5ecfb6334904f6058d6d376d21b5efc438 (patch) | |
| tree | 3573f744b6d7c33f55dd06a152d4ff199cf30b22 /techlibs | |
| parent | b3155af5f65333d272da339222e1e1962fb088b7 (diff) | |
| download | yosys-721f1f5ecfb6334904f6058d6d376d21b5efc438.tar.gz yosys-721f1f5ecfb6334904f6058d6d376d21b5efc438.tar.bz2 yosys-721f1f5ecfb6334904f6058d6d376d21b5efc438.zip | |
Added basic support for $expect cells
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/common/simlib.v | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index 342555024..ea36e2922 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -1305,6 +1305,22 @@ endmodule // -------------------------------------------------------- +module \$expect (A, EN); + +input A, EN; + +`ifndef SIMLIB_NOCHECKS +always @* begin + if (A === 1'b1 && EN === 1'b1) begin + $display("Expectation %m passed."); + end +end +`endif + +endmodule + +// -------------------------------------------------------- + module \$equiv (A, B, Y); input A, B; |