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| author | whitequark <whitequark@whitequark.org> | 2016-07-10 14:41:34 +0000 | 
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2016-07-10 15:46:46 +0000 | 
| commit | c0645839fe499fbc37199744cab5c624e5840dba (patch) | |
| tree | d7c48382fcba7a5b798fe7bdfd7f079a6cbcd807 /techlibs | |
| parent | b5a9fba0db5a8f29cffa22aa61f9d9cb7f69009a (diff) | |
| download | yosys-c0645839fe499fbc37199744cab5c624e5840dba.tar.gz yosys-c0645839fe499fbc37199744cab5c624e5840dba.tar.bz2 yosys-c0645839fe499fbc37199744cab5c624e5840dba.zip | |
greenpak4: add GP_COUNT{8,14}_ADV cells.
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/greenpak4/cells_sim.v | 26 | 
1 files changed, 26 insertions, 0 deletions
| diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index be8e66c66..67f00f3a4 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -94,6 +94,32 @@ module GP_COUNT14(input CLK, input wire RST, output reg OUT);  endmodule +module GP_COUNT8_ADV(input CLK, input RST, output reg OUT, +                     input UP, input KEEP); + +	parameter RESET_MODE 	= "RISING"; +	parameter RESET_VALUE   = "ZERO"; + +	parameter COUNT_TO		= 8'h1; +	parameter CLKIN_DIVIDE	= 1; + +	//more complex hard IP blocks are not supported for simulation yet + +endmodule + +module GP_COUNT14_ADV(input CLK, input RST, output reg OUT, +                      input UP, input KEEP); + +	parameter RESET_MODE 	= "RISING"; +	parameter RESET_VALUE   = "ZERO"; + +	parameter COUNT_TO		= 14'h1; +	parameter CLKIN_DIVIDE	= 1; + +	//more complex hard IP blocks are not supported for simulation yet + +endmodule +  module GP_DELAY(input IN, output reg OUT);  	parameter DELAY_STEPS = 1; | 
