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| author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-12-10 13:57:37 +0800 |
|---|---|---|
| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-12-10 13:57:37 +0800 |
| commit | 797c03997e2e87416d7486197b079b6c273e2fa6 (patch) | |
| tree | 0f40e5610b5c3b8f416f009b062841003564c6dc /techlibs | |
| parent | 8767cdcac95d30a454ba2bdd7c0d81083d3215ec (diff) | |
| download | yosys-797c03997e2e87416d7486197b079b6c273e2fa6.tar.gz yosys-797c03997e2e87416d7486197b079b6c273e2fa6.tar.bz2 yosys-797c03997e2e87416d7486197b079b6c273e2fa6.zip | |
greenpak4: Inverted D latch cells now have nQ instead of Q as output port name for consistency
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/greenpak4/cells_sim.v | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index a59d17154..ca3e6cdbf 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -249,12 +249,12 @@ module GP_DLATCH(input D, input nCLK, output reg Q); end endmodule -module GP_DLATCHI(input D, input nCLK, output reg Q); +module GP_DLATCHI(input D, input nCLK, output reg nQ); parameter [0:0] INIT = 1'bx; - initial Q = INIT; + initial nQ = INIT; always @(*) begin if(!nCLK) - Q <= ~D; + nQ <= ~D; end endmodule @@ -269,14 +269,14 @@ module GP_DLATCHR(input D, input nCLK, input nRST, output reg Q); end endmodule -module GP_DLATCHRI(input D, input nCLK, input nRST, output reg Q); +module GP_DLATCHRI(input D, input nCLK, input nRST, output reg nQ); parameter [0:0] INIT = 1'bx; - initial Q = INIT; + initial nQ = INIT; always @(*) begin if(!nRST) - Q <= 1'b1; + nQ <= 1'b1; else if(!nCLK) - Q <= ~D; + nQ <= ~D; end endmodule @@ -291,14 +291,14 @@ module GP_DLATCHS(input D, input nCLK, input nSET, output reg Q); end endmodule -module GP_DLATCHSI(input D, input nCLK, input nSET, output reg Q); +module GP_DLATCHSI(input D, input nCLK, input nSET, output reg nQ); parameter [0:0] INIT = 1'bx; - initial Q = INIT; + initial nQ = INIT; always @(*) begin if(!nSET) - Q <= 1'b0; + nQ <= 1'b0; else if(!nCLK) - Q <= ~D; + nQ <= ~D; end endmodule @@ -314,15 +314,15 @@ module GP_DLATCHSR(input D, input nCLK, input nSR, output reg Q); end endmodule -module GP_DLATCHSRI(input D, input nCLK, input nSR, output reg Q); +module GP_DLATCHSRI(input D, input nCLK, input nSR, output reg nQ); parameter [0:0] INIT = 1'bx; parameter[0:0] SRMODE = 1'bx; - initial Q = INIT; + initial nQ = INIT; always @(*) begin if(!nSR) - Q <= ~SRMODE; + nQ <= ~SRMODE; else if(!nCLK) - Q <= ~D; + nQ <= ~D; end endmodule |