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| author | Clifford Wolf <clifford@clifford.at> | 2016-07-27 15:41:22 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-07-27 15:41:22 +0200 |
| commit | 40563129872f5a2287f54cb0dbd79534b493a5d6 (patch) | |
| tree | 0ef8462549bafba7356efd94570a19d230b68af9 /techlibs | |
| parent | a7b07696238dbfd8e4fb5fd41d597200abef4909 (diff) | |
| download | yosys-40563129872f5a2287f54cb0dbd79534b493a5d6.tar.gz yosys-40563129872f5a2287f54cb0dbd79534b493a5d6.tar.bz2 yosys-40563129872f5a2287f54cb0dbd79534b493a5d6.zip | |
Added $anyconst and $aconst
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/common/simlib.v | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index 8ab124034..ac4269c90 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -1330,6 +1330,30 @@ endmodule // -------------------------------------------------------- +module \$aconst (Y); + +parameter WIDTH = 0; + +output [WIDTH-1:0] Y; + +assign Y = 'bx; + +endmodule + +// -------------------------------------------------------- + +module \$anyconst (Y); + +parameter WIDTH = 0; + +output [WIDTH-1:0] Y; + +assign Y = 'bx; + +endmodule + +// -------------------------------------------------------- + module \$equiv (A, B, Y); input A, B; |